Top Tech Jobs & Startup Jobs in Los Angeles, CA

Lead developer relations with US national labs and federal research: build strategic collaborations, embed NVIDIA quantum SDKs, run workshops and trainings, present at conferences, create reference implementations, and relay research needs to product and engineering teams to drive adoption of CUDA-Q, cuQuantum, CUDA-Q QEC, and NVQLink.

Build, scale, and harden deep learning training infrastructure for multi-thousand GPU clusters. Improve data loaders, distributed training, scheduling, and performance monitoring. Develop fault-resilient orchestration, training pipelines for massive video datasets, and collaborate with researchers and platform teams to maximize training efficiency, availability, and scalability.

Own strategy and execution for a portfolio of AI-native and hyperscale customers. Serve as primary relationship owner, drive revenue, market share and product adoption, coordinate with solution architects, product marketing, OEMs and partners, forecast and train customers, and evangelize NVIDIA platforms to accelerate enterprise growth.

Lead planning and execution for GPU-accelerated data science and processing libraries. Drive cross-functional release and compliance programs, manage dependencies and risks, improve dev processes and tooling, build program metrics, and ensure high-quality, predictable open-source releases.

Design, build, and maintain scalable infrastructure and CI/CD pipelines for TensorRT Edge-LLM across embedded and desktop GPU/CPU platforms. Configure and operate tools (CMake, GitLab, GitHub Actions, Kubernetes, Docker), monitor systems, automate builds/tests, address security CVEs, and collaborate with autonomy and external partners to improve development velocity and reliability.

Design and optimize high-speed, high-density ASIC package layouts and substrate breakouts. Perform pinout optimization, routing, placement, stack-up, power distribution, CAD library development, feasibility studies, and productivity methodology improvements while collaborating with package leads and cross-functional teams.

Design and perform physical layout for silicon interposers using Cadence Virtuoso; run DRC/LVS and verification (Calibre, ICV, Thunder); perform feasibility studies, floorplanning, custom layout, and collaborate with package, SI, and technology teams to meet schedule, cost, manufacturability, and electrical goals.

Lead design and development of infrastructure, automation frameworks, and internal developer tools. Build scalable services, APIs, dashboards, workflow engines, and LLM-powered workflows integrated with CI/CD, source control, test infrastructure, and observability. Define architecture and reliability practices, mentor engineers, review designs, and provide technical leadership for automation and tooling projects.

Optimize large-scale AI inference performance by designing reproducible experiments, profiling GPU workloads, tuning serving configurations (batching, KV cache, quantization, parallelism), and delivering fixes upstream (framework patches, kernels, deployment recipes) across TensorRT-LLM, vLLM, SGLang and related stacks.

Lead HBM and LPDDR system integration and bringup for next-generation SoCs. Own memory performance, power, thermal, and reliability closure across silicon, package, board, and firmware. Drive post-silicon margining, VF shmoo, eye characterization, and correlation. Debug training, calibration, SI/PI, and system stability issues. Define validation, characterization, and issue-tracking plans to produce production-ready operating points.