Top Tech Jobs & Startup Jobs in Los Angeles, CA

Provide EDA/CAD support for SiGe and CMOS high-speed analog/mixed-signal ASIC design. Install, customize, and support vendor PDKs and CAD tools, develop design standards and flows, execute layout, archive and tapeout, and support engineering users and license/tool infrastructure.

As a Senior Electrical PCB Layout Designer, you will design high-speed PCB layouts, collaborate with engineers, and optimize layouts for performance while ensuring manufacturability.

Lead the qualification and process development for a new InP photonics semiconductor fabrication facility, focusing on process integration and yield improvement.

As an Applied R&D Engineer, you will develop backend application software in a Kubernetes environment, focusing on streaming APIs, system design, and code quality.

As a Principal/Staff Software Engineer, you will design, implement, and lead embedded software for Optical DCI transport systems, ensuring performance and reliability.

Responsible for managing wafer level testing processes to improve yield, overseeing test equipment, and coordinating with external suppliers and engineering teams.

Develop commercial strategy, build pricing models and quotes, respond to RFPs for Fixed Networks products, create BOMs, support sales/pre-sales with pricing and deal structuring, analyze commercial risks, and improve commercial tools and processes to protect profitability.

The Head of RE Labs & Fabs Infrastructure will develop strategic infrastructure plans, oversee governance, manage projects, ensure operational excellence, and foster cross-functional collaboration to enhance lab, manufacturing, and data center environments.

Senior, customer-facing technical leader who defines and governs end-to-end solution architectures and multi-year technology roadmaps for a large CSP. Engages with customer CxOs, aligns cross-BG architecture across network, cloud, and IT, supports value-based selling with ROI/TCO models, and drives innovation and co-creation with product, R&D, and delivery teams.

Lead reliability activities for photonic integrated circuits (PICs): evaluate failure modes, coordinate accelerated stress tests, develop life models from aging-data, and drive failure mode analyses across design, development, and production teams.