Owner of micro-architecture and RTL lifecycle for complex digital blocks. Implement RTL in SystemVerilog/Verilog, drive control logic and IP integration, support sign-off (CDC, RDC, lint, synthesis), collaborate with DV teams for closure and debug, and take full project ownership with minimal supervision.

Lead RTL design and micro-architecture for complex digital blocks using SystemVerilog/Verilog. Implement control logic, integrate IPs, support SoC integration, and drive sign-off activities (CDC/RDC/lint/synthesis). Collaborate with DV teams for closure and debug and own the full project lifecycle with minimal supervision.

Remote 12-month contract RTL Design Engineer to own micro-architecture and RTL implementation for complex digital blocks. Requires SystemVerilog/Verilog expertise, memory controller and SoC integration experience, IP integration, multi-clock-domain design, and sign-off familiarity (CDC/RDC/lint/synthesis). Works independently and collaborates with DV for closure and debug.