Top Tech Jobs & Startup Jobs in Los Angeles, CA

Partner with industry and account teams to design and deliver NVIDIA-based AI, HPC, and GPU/networking solutions for industrial robotics. Engage customers and partners, produce technical documentation and samples, support deployments both in datacenters and at the edge, and lead technical engagements with lighthouse customers and solution partners.

Serve as a customer-facing solutions architect for CAE/CFD/FEA ISVs and OEMs, accelerating simulation and digital-twin workflows on NVIDIA platforms. Advise on GPU-acceleration, physics-informed ML/surrogate modeling, Omniverse integration, architecture analysis, and deliver trainings, demos, and prototypes to improve performance and simulation cycles.

Lead technical engagements to integrate NVIDIA GPU, networking, and AI platforms into industrial robotics solutions. Partner with customers, partners, and internal teams to design, document, and deliver scalable AI/HPC datacenter and edge architectures, provide technical guidance, and create samples, whitepapers, and demos.

Design and scale Kubernetes-native, GPU-accelerated cloud architectures for large-scale robotics simulation, synthetic data pipelines, training, and inference. Advise partners, optimize scheduling, storage, networking, and GPU utilization, and drive adoption of NVIDIA Physical AI frameworks while collaborating with product and engineering teams.

Develop algorithms and optimizations for inference and compiler stack, enhance performance metrics, collaborate with hardware teams, and publish work on novel approaches.

Develop and implement compiler optimization algorithms for deep learning workloads, analyze networks, debug and profile GPU performance (CUDA), define public APIs, and deliver ahead-of-time and just-in-time compilation techniques for NVIDIA GPUs to improve inference performance, build times, and memory efficiency.

Design and implement RTL and system-level SoC modules, perform logic synthesis and timing analysis, integrate modules into SOC, collaborate with architects and verification teams, support silicon bring-up, and improve design flows and methodologies to enhance efficiency and chip yield.

Lead invention of AI-driven ASIC development methodology, identify cross-stage bottlenecks, build scalable data pipelines, define metrics, mentor engineers, and evaluate AI/EDA research to improve predictability and cycle time.

Lead developer relations with US national labs and federal research: build strategic collaborations, embed NVIDIA quantum SDKs, run workshops and trainings, present at conferences, create reference implementations, and relay research needs to product and engineering teams to drive adoption of CUDA-Q, cuQuantum, CUDA-Q QEC, and NVQLink.

Build, scale, and harden deep learning training infrastructure for multi-thousand GPU clusters. Improve data loaders, distributed training, scheduling, and performance monitoring. Develop fault-resilient orchestration, training pipelines for massive video datasets, and collaborate with researchers and platform teams to maximize training efficiency, availability, and scalability.