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Serve as a technical advisor for semiconductor customers and EDA developers to GPU-accelerate EDA and manufacturing workflows, apply ML/DL for inspection and yield, analyze architectures for acceleration, deliver trainings/demos, and collaborate with product and engineering teams to deploy scalable AI-enabled solutions.

Design and optimize high-performance C++/CUDA libraries for GPU-based data processing. Improve multi-node GPU communication (UcxExchange), optimize Presto GPU query performance, and lead enhancements across Presto, Velox, and cuDF projects for efficient DataFrame and database acceleration.

Design and implement an MLIR-based AI compiler for GPU inference: develop graph representations and dialects, optimize performance and memory, define APIs, generate kernels, and collaborate with framework and hardware teams to enable new model patterns and GPU features.

Analyze and optimize HPC application performance across CPU and multi-node multi-GPU systems by driving compiler and library improvements. Port and tune applications, evaluate compiler/runtime/driver impacts, and collaborate with compiler development and application engineering teams to deliver performance enhancements.

Lead cross-stack adoption of modern toolchains, build and code-health practices, and performance workflows on NVIDIA CPU platforms. Integrate and validate compilers, linkers, cross-compilation, and CI; profile and optimize large codebases; build automation and playbooks; drive integration blockers to owners and communicate measurable before-and-after results to engineering teams and leadership.

Technical leader who bridges product engineering and operations for networking semiconductors. Ensures manufacturing readiness, monitors yield and risks, coordinates cross-functional issue resolution, supports NPI-to-mass-production transitions, and communicates product health to engineering, operations, supply chain, and executives.

Develop and implement compiler optimization algorithms and code generation for deep learning workloads (XLA/OpenXLA) targeting NVIDIA GPUs. Design graph partitioning and tensor sharding for distributed training/inference, performance tune models, work with ML frameworks (JAX) and hardware teams, and contribute to compiler/tooling (MLIR/LLVM/Triton).

Design, develop, and operate large-scale SDN control and data plane software (OVS/OVN/OpenFlow) for NVIDIA AI Cloud. Build network orchestration and IaC (gRPC/REST, Ansible, Terraform, ArgoCD/Flux), maintain CI/CD pipelines, implement observability/monitoring, drive upstream open-source contributions, and collaborate with SRE/DevOps to ensure production reliability and performance SLAs.

The role involves designing and optimizing GPU architectures for AI Inference, analyzing hardware-software relationships, and developing performance models.

The Senior Circuit Design Engineer will improve netlist and timing quality in deep submicron technologies, collaborate on circuit design, and mentor junior engineers.