Top Tech Jobs & Startup Jobs in Los Angeles, CA

Lead EMI/EMC testing for satellite electronics, define compliance standards, collaborate with engineers to improve designs, and manage test campaigns for certification.

Lead manufacturability and production ramp for large satellite subsystems: define production-ready build flows, tooling, and capacity; lead first-article builds and flight hardware integration; deploy advanced manufacturing and automation; mentor junior engineers; drive DFM and continuous improvement to reduce cost, risk, and cycle time.

The Senior HR Business Partner will shape K2 Space's culture and people strategy, ensuring compliance with labor laws and fostering a positive work environment.

The Senior Satellite Mechanical Engineer will lead the design and analysis of mechanical structures for satellites, collaborating with cross-functional teams, and managing hardware development and testing.

The Principal GNC Engineer will drive spacecraft GNC architecture, perform verification and validation, develop tools and algorithms, and support launch operations, while mentoring engineers.

Lead ASIC package architecture and detailed FC-BGA/MCM package designs for high-pin-count, high-speed, power-dense SoCs. Drive package trade studies (SI/PI, thermal, manufacturability, reliability), define standards, collaborate with silicon/RF/systems teams, work with OSATs and substrate vendors, and support qualification and production ramp.

Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.

Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.

The role involves leading ASIC package design for FC-BGA and MCM solutions, ensuring high-performance mixed-signal/digital SoCs succeed from architecture to production. Responsibilities include trade studies, design standards, and vendor collaboration.

Lead verification of custom ASIC/SoC from block to full-chip: develop verification plans, build SystemVerilog/UVM testbenches, run constrained-random and directed tests, use SVA and formal methods, manage regressions and CI, drive coverage closure, support post-silicon bring-up, and influence DV methodology across cross-functional teams.