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Lead the integration of AI in CPU/SoC design and verification. Build AI copilots for workflows, partner with EDA vendors, and define methodologies for CPU design improvement.

As a Recruiting Coordinator, you will manage interview logistics, maintain candidate data, and support the recruiting team for smooth operations.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.

The HPC Architect will design and implement cutting-edge architectures for scientific and data-intensive applications, collaborating with engineers to optimize HPC performance.

The Staff DevOps Engineer will optimize infrastructure for chip development, build CI/CD pipelines, and enhance workflows using AI/ML practices.

The CPU Workload Performance Analysis Engineer will conduct workload characterization and performance simulation to optimize CPU products, collaborating with architects and designers.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

The role involves defining and implementing CPU system RTL, collaborating with teams on delivering functional and efficient CPU designs, and optimizing power, performance, and area.

Lead end-to-end software development for Chiplet-based SiP, manage multi-year software roadmaps, and coordinate teams across silicon and firmware.