Top Tech Jobs & Startup Jobs in Los Angeles, CA

Design and implement chip-level DFT strategies for high-speed CPU cores and multi-chiplet SiP. Implement and verify scan chains, memory BIST, and JTAG. Partner with RTL, physical design, and verification teams. Script and automate DFT flows using EDA tools (ATPG, fault coverage) and support SoC-level silicon debug, formal verification, and DFT signoff.

Contract recruiter responsible for full-cycle hiring for supply chain, procurement, manufacturing operations, logistics, supplier quality, planning, and business operations. Build talent pipelines beyond LinkedIn, partner with hiring managers to scope roles and move searches, assess and close candidates, and maintain process-oriented, scalable recruiting workflows. 6-month contract, remote with location preferences.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.

Build and maintain infrastructure automation, integrations, and SRE tooling. Develop backend services, infrastructure-as-code, observability, and provisioning for bare metal, VMs, and Kubernetes. Collaborate with hardware, software, and AI teams, drive operational excellence, and provide technical leadership.

Lead and grow a software engineering team focused on RISC-V software ecosystem, collaborating with teams to establish RISC-V as the standard.

Run deal governance, escalation management, and cross-functional coordination to remove blockers and accelerate sales execution. Partner with Sales, Legal, Finance, Trade Compliance, and Operations to manage deal logistics, contract review, forecast support, S&OP, incentive reconciliation, and CRM-driven processes to scale GTM operations.

Lead architecture and microarchitecture of RISC-V CPU vector, floating-point, and matrix extensions. Translate HPC/AI workload needs into scalable CPU designs, optimize performance/power/area, define architectural specs, lead cross-functional teams from concept through silicon, and work on RTL development to enable efficient heterogeneous compute for AI/HPC.

The Performance Architect will work on high-performance systems with expertise in software and hardware, focusing on AI and HPC solutions.

As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.

Own Tenstorrent's developer platform including firmware, system software, packaging, updates, and a unified CLI. Define roadmap, prioritize engineering work, partner with DevRel and customers, ship iterative improvements, and measure success via developer NPS and CLI adoption.