Top Tech Jobs & Startup Jobs in Los Angeles, CA

Own the flagship data-center AI compute product line: define topology, cabling, power, and orchestration; coordinate engineering, manufacturing, CX and sales; ensure reliable deployments in colos and customer data centers; support hardware, software, and firmware in the field; travel for installs and customer engagements; drive uptime, scaling, and total cost of ownership improvements.

Lead and grow a software engineering team focused on RISC-V software ecosystem, collaborating with teams to establish RISC-V as the standard.

The Performance Architect will work on high-performance systems with expertise in software and hardware, focusing on AI and HPC solutions.

As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.

Lead as a hybrid Chief of Staff and execution-focused TPM for the RISC-V software org: define goals, plan and track execution, manage dependencies and risks, drive cross-functional initiatives, support headcount and recruiting, prepare leadership materials, and represent the team to partners and customers.

Design board-level routing studies, mock-ups, and SI/PI modeling to support early-stage semiconductor package and package-board co-design. Collaborate with signal integrity, power integrity, mechanical, and system teams to develop PCB routing environments for BGA optimization, package escape studies, and system-level electrical modeling. Apply engineering judgment to evaluate tradeoffs and improve workflows using automation and data analytics.

Contract Technical Recruiter (12-month, hybrid in Austin) partnering with engineering leaders to source, attract, and hire AI/ML, systems software, and hardware engineering talent. Build hiring strategies, talent pipelines, and targeted sourcing campaigns, deliver a high-touch candidate experience, and share market intelligence to improve recruiting outcomes.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.