Top Remote Senior Level Hardware Engineer Jobs in Los Angeles, CA

The Senior Mechanical Engineer will design and develop consumer products, collaborate with teams, and lead mechanical engineers in creating and testing innovative technologies.

The Senior Mechanical Engineer will design projects, oversee client interactions, manage project budgets, and ensure quality and compliance in engineering practices.

Lead the IC packaging team to develop advanced packaging solutions, manage product cycles, and ensure design for manufacturability while collaborating on simulations and qualifications.

The Mechanical Engineering Director leads the U.S. Data Center Mechanical Department, providing oversight, technical direction, and mentorship for engineers. Responsibilities include managing design standards, supporting project delivery, and ensuring compliance with applicable codes and best practices.

The Lead RTL/FPGA Design Engineer will develop and manage high-performance coherent modems for free space optical communications, translating DSP algorithms into synthesizable RTL, ensuring compliance, and supporting integration and testing.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.

This role involves leading optical test engineering projects, developing test protocols, mentoring engineers, and ensuring compliance in testing systems. You will work on system-level test station development and integrate new technologies for quality improvement and scalability.

The Principal Engineer at CIRCOR Aerospace & Defense leads fluid control product development, provides technical guidance, and mentors engineers to drive innovation and excellence.

Lead the functional verification of advanced ASICs, overseeing test planning, execution, and coverage analysis, while collaborating with various teams.

Execute synthesis, place-and-route and STA for ASIC partitions from RTL to silicon. Collaborate with architects, RTL designers and DFT engineers to close EM/IR, LEC and physical verification signoff. Improve physical design methodologies (synthesis, PnR, EMIR, PDN), troubleshoot flows and work with EDA vendors to resolve issues while meeting tight schedules and low-power goals.