Top Remote Senior Level Hardware Engineer Jobs in Los Angeles, CA

The Lead Mechanical Engineer will manage tooling design for hydropower projects, ensuring compliance with safety and engineering standards, coordinating with various teams and performing technical calculations.

Lead development of behavioral models and mixed-signal verification methodology for analog/mixed-signal SoCs. Create Verilog/SystemVerilog/Verilog-AMS models, build co-simulation testbenches, integrate AMS into UVM digital environments, support architectural exploration, and drive cross-functional alignment with RF, analog, and digital teams to ensure successful silicon tapeout and bring-up.

Develop innovative physical design methodologies for GPUs and SOCs, focusing on PPA improvements and collaboration across multiple teams. Use AI/ML to enhance design efficiency.

Responsible for evaluating and ordering manufacturing equipment, overseeing installation and maintenance, providing technical support, and writing maintenance schedules.

Seeking an experienced DFT Verification Engineer to ensure ASIC DFT logic correctness, building robust verification environments, and collaborating with design engineers on high-quality silicon delivery.

The Staff Process Integration Engineer will lead process development for superconducting IC fabrication, optimize production processes, and enhance reliability in collaboration with foundries.

As an ASIC Design Verification Engineer, you will develop and execute verification strategies for AI inference ASICs, ensuring functional correctness and performance, while collaborating with design and architecture teams.

Lead PCB/FPC design for consumer electronics: component placement, routing, signal and power integrity analysis, DFM, and producing fabrication/assembly packages. Manage vendors, release designs into PLM, author ECOs, and maintain ECAD libraries.

Owner of micro-architecture and RTL lifecycle for complex digital blocks. Implement RTL in SystemVerilog/Verilog, drive control logic and IP integration, support sign-off (CDC, RDC, lint, synthesis), collaborate with DV teams for closure and debug, and take full project ownership with minimal supervision.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.