Jobs at OMNIVISION

Designs sensor timing logic and ISP data paths, contributes to SoC architecture, and performs chip integration and verification. Collaborates on physical design, timing closure, DFT, chip bring-up, silicon debugging, image tuning, and production qualification. Requires at least two years of RTL digital design experience with Verilog or SystemVerilog, scripting proficiency, and experience optimizing power, performance, and area. Image sensor, MIPI, and ISP experience are preferred.

Design and integrate digital circuit logic for image sensor and ISP systems, including sensor timing control, data paths, chip architecture, and SoC integration. Collaborate on PPA optimization, physical design, timing closure, DFT, verification, silicon bring-up, debugging, and image quality tuning. Support validation and production readiness while working with analog, digital, algorithm, and application engineering teams.

Designs and integrates digital circuits for image sensors, including sensor timing control and ISP data pipelines. Responsibilities include chip architecture, RTL design, verification, synthesis, timing closure, DFT, full-chip integration, silicon validation, debugging, image tuning, and customer support. The role collaborates with analog, backend, algorithm, and application engineering teams throughout the ASIC development lifecycle.

Characterize and optimize CMOS image sensor performance by bringing up new silicon, validating functionality, developing testing methodologies, analyzing pixel-level and analog/digital subsystems, and identifying improvements. Collaborate with design, process, applications, production, and quality teams to resolve system issues, yield and reliability problems, and transition new products into production.

Design and develop CMOS image sensor analog and mixed-signal circuits, including transistor-level schematics, layouts, floorplans, readout circuits, and interfaces. Simulate and verify designs using industry-standard EDA tools, perform DRC, LVS, PERC, and IR-drop checks, and collaborate cross-functionally to debug and optimize fabricated image sensors. Analyze specifications such as speed, noise, linearity, and power while accounting for process variation and operating-condition corners.

Design and integrate RTL digital logic for image sensor and ISP systems. Responsibilities include chip architecture, sensor timing, image data paths, PPA optimization, physical design collaboration, DFT, verification, chip integration, silicon bring-up, debugging, and image quality tuning. The role requires collaboration with analog, digital, algorithm, application, and physical design teams throughout production readiness.

Design and integrate digital circuit logic for image sensor and ISP systems. Responsibilities include chip architecture, RTL implementation, ISP data-path integration, PPA optimization, physical design collaboration, verification, chip bring-up, silicon debugging, and image quality tuning. The role works closely with sensor, algorithm, application, and physical design teams to achieve production readiness.

Designs transistor-level analog and mixed-signal circuits for CMOS image sensors, including block and whole-chip simulation, layout optimization, verification, debugging, characterization, and performance improvement. Collaborates with verification, process, test, and applications teams to bring image sensor products from concept through release. Conducts circuit R&D, proposes technical solutions, and guides less experienced engineers.