Teams at OMNIVISION

Designs sensor timing logic and ISP data paths, contributes to SoC architecture, and performs chip integration and verification. Collaborates on physical design, timing closure, DFT, chip bring-up, silicon debugging, image tuning, and production qualification. Requires at least two years of RTL digital design experience with Verilog or SystemVerilog, scripting proficiency, and experience optimizing power, performance, and area. Image sensor, MIPI, and ISP experience are preferred.

Design and integrate digital circuit logic for image sensor and ISP systems, including sensor timing control, data paths, chip architecture, and SoC integration. Collaborate on PPA optimization, physical design, timing closure, DFT, verification, silicon bring-up, debugging, and image quality tuning. Support validation and production readiness while working with analog, digital, algorithm, and application engineering teams.

Designs and integrates digital circuits for image sensors, including sensor timing control and ISP data pipelines. Responsibilities include chip architecture, RTL design, verification, synthesis, timing closure, DFT, full-chip integration, silicon validation, debugging, image tuning, and customer support. The role collaborates with analog, backend, algorithm, and application engineering teams throughout the ASIC development lifecycle.