The job description provides no responsibilities or qualification details beyond the title. The role is identified as a senior-level analog design engineering position.
About the Role
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Artificial Intelligence • Hardware • Machine Learning • Semiconductor
Designs and verifies analog and mixed-signal circuits for AI hardware, from SPICE simulations through top-level algorithm modeling in Python and SystemVerilog. Owns interface specifications, cross-functional co-verification, calibration and test algorithms, and chip-level concerns including EM/IR, ESD, and power distribution. Relevant work includes ADC/DAC, PLL, SERDES, sensing, digital controllers, and high-reliability or automotive systems.
Top Skills:
AdcCadence VirtuosoDacEm/IrEsdLinuxMatlabNumpyPllPythonReal Number ModelingSerdesSpiceSystemverilog
Artificial Intelligence • Cloud • Information Technology • Software
Designs, implements, and validates high-speed analog and mixed-signal integrated circuits for silicon photonics and optical interconnect products. Responsibilities include circuit architecture, block-level design, full-chip integration, collaboration with digital and multidisciplinary teams, post-silicon test planning, and technical documentation. The role focuses on low-voltage, low-power circuits supporting next-generation data center connectivity, including amplifiers, drivers, equalizers, PLLs, CDRs, TIAs, and optical modulator drivers.
Top Skills:
AdcsAmplifiersAnalog Integrated CircuitsBicmosClock And Data Recovery CircuitsCmosDacsDeep-Submicron Process TechnologiesDriversEqualizersEsd DesignHigh-Speed Serial LinksInductorsMixed-Signal Integrated CircuitsNrzOptical InterconnectsOptical Modulator DriversPackage DesignPam4Phase InterpolatorsPllsPost-Silicon TestingSilicon PhotonicsTransimpedance AmplifiersTransmission Lines
Artificial Intelligence • Hardware • Software • Nanotechnology • Semiconductor • Quantum Computing • Defense
Lead analog and mixed-signal verification for cryogenic CMOS quantum-control circuits. Develop AMS verification strategies, behavioral models, SystemVerilog/UVM environments, assertions, regressions, and coverage methodologies. Perform transistor-level simulations, corner and Monte Carlo analysis, model correlation, DFT verification, silicon bring-up, lab debugging, and measurement validation. Automate workflows with scripting and maintain Git/Jenkins continuous integration. Collaborate across design, modeling, DFT, digital verification, and validation teams from block development through tape-out.
Top Skills:
AdcsCadence Ams DesignerCadence VirtuosoCmosContinuous IntegrationDacsDftEldoGitHspiceJenkinsLdosMatlabMonte Carlo SimulationPerlPllsPmicsPslPvt AnalysisPythonSerdesSpectreSpectre AmsSpiceSv-RnmSvaSystemverilogTclUvmUvm-AmsVerilog-AVerilog-AmsWrealXcelium
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