Teams at System Canada Technologies

Create feature descriptions, installation manuals, help files, and user guides for IPedge/VIPedge IP-PBX. Develop documentation by interacting with systems, interviewing developers and QA, reviewing specs, and producing diagrams and charts.

Perform synthesis and static timing analysis (STA) for complex SoCs, drive timing closure, write TCL/Perl automation scripts, generate timing constraints at block and top levels, and perform formal equivalency checking (LEC/Formality). Collaborate closely with logic and physical design teams; low-power design and DFT knowledge are a plus.

Perform full-chip and block-level physical design from netlist handoff to GDS tapeout: floorplanning, place-and-route, CTS, timing closure, physical verification, IR/crosstalk/EM analysis, automation via TCL/Perl, and collaborate with logic designers on complex SoCs using low-power techniques.