Senior Principal Optical Modeling Architect

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

What You Can Expect

The High-Speed Optical Modeling Architect will be responsible for designing, simulating, and analyzing high-speed electrical & optical systems and components. This includes the development of optical models, the integration of photonic devices with electronic systems, and optimizing performance for high-bandwidth and low-latency applications. You will play a key role in advancing optical communication technologies, helping drive the next generation of optical interconnects, co-packaged optics, and high-performance networks.

Modeling and Simulation of Optics Drivers:

Develop models for high-speed optical drivers used to drive Silicon Photonic (SiPho) modulators (e.g., Mach-Zehnder modulators (MZM), VCSELs).

Model the electrical characteristics of optical drivers to ensure the proper transmission of high-speed signals to optical modulators.

Focus on key parameters like pulse shaping, voltage swing, and rise/fall time to achieve the required data rates (e.g., 100 Gbps or higher).

Simulate the performance of the optical driver under various operating conditions, including temperature variations and voltage fluctuations.

Transimpedance Amplifier (TIA) Modeling:

Develop models for TIA circuits, which convert the photocurrent generated by photodetectors (e.g., PIN diodes, avalanche photodiodes (APDs)) into a voltage signal.

Model key aspects of TIAs, including feedback resistors, bandwidth, noise characteristics, and linearity to ensure high sensitivity and low distortion.

Analyze the impact of thermal noise, shot noise, and jitter on TIA performance in high-speed applications.

SerDes I/O System Modeling:

Develop accurate and efficient models for high-speed SerDes interfaces, focusing on both the transmitter and receiver.

Model the electrical behavior of high-speed I/O circuits, considering factors like clock data recovery (CDR), equalization, and voltage swing.

Use simulation tools (e.g., Cadence, Keysight ADS, Synopsys HSPICE) to simulate the performance of SerDes systems in both ideal and non-ideal conditions.

Signal Integrity Analysis:

Perform signal integrity simulations, including eye diagram analysis, bit error rate (BER) analysis, and jitter analysis for SerDes I/O interfaces.

Model and analyze the impact of noise, crosstalk, skew, and reflections on the signal quality and timing in high-speed links.

Implement and simulate techniques like channel equalization, pre-emphasis, and de-emphasis to mitigate signal degradation.

What We're Looking For

Educational Background:

• A PhD or Master’s degree in Optical Engineering, Electrical Engineering, or a related field with significant experience in optical communications and high-speed systems.

Experience:

• Proven experience (typically 10+ years) in high-speed SerDes modeling, Optucal modelling, signal integrity analysis, and I/O system design.
• Experience working with high-speed communication protocols such as PCIe, Ethernet is a MUST.
• Experience with SerDes I/O performance at speeds of100 Gbps, 200Gbps and beyond is highly preferred.
• Experinece with modelling of Opto electronic components such as Silicon Photonics Driver, TIA is highly preferred

Programming and Tools:

• Proficiency in programming languages such as Python, C++, or Matlab for automation, data analysis, and creating custom simulations.
• Experience with simulation tools (e.g., Cadence, Keysight ADS, Synopsys HSPICE) for circuit and system-level modeling of high-speed I/O systems.

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.