Senior Design Automation Engineer - Front End Design Verification

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Altera is seeking a Senior Design Automation Engineer to join our Design Methodology, Automation and Infrastructure Team. 

This team is responsible for building and maintaining the core automation infrastructure that supports Altera’s FPGA design flows—from RTL to GDSII. In this role, you will play a critical part in scaling our internal design productivity, delivering highly automated, reliable, and efficient flow systems that accelerate development cycles for next-generation FPGA products.
 

Key Responsibilities of the Senior Design Automation Engineer include but are not limited to:

• Develop, deploy, and support advanced design automation flows and methodologies for digital semiconductor design.

• Create scripts, tooling customizations, and automation frameworks leveraging AI-driven tools and systems to streamline complex design processes.

• Evaluate, integrate, and enhance EDA tools to improve design productivity, efficiency, and quality across the organization.

• Automate repetitive design tasks, delivering solutions that are robust, scalable, maintainable, and aligned with long-term architecture.

• Collaborate with design and verification teams to identify workflow bottlenecks and implement impactful process improvements.

• Drive continuous improvement in design automation infrastructure, methodologies, and best practices.

• Work closely with internal teams and external EDA vendors to resolve tool issues, influence roadmaps, and adopt new capabilities.

Salary Range 

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.  

$187,900 - $270,700 USD 

We use artificial intelligence to screen, assess, or select applicants for the position.  Applicants must be eligible for any required U.S. export authorizations. 

#LI-MD1

Minimum Qualifications:

Bachelor’s or Master’s Degree in Computer Science, Electrical Engineering, or related field with 8+ years of relevant industry experience, including:

• 8+ years of hands-on experience with Front End RTL and or Design Verification EDA tools and FPGA/ASIC design flows (e.g.,VCS, Xcelium, SpyGlass).

• Experience utilizing AI/ML-driven features within commercial EDA tools and/or building data pipelines and training systems to support learning-based design automation.

• Proficiency in Unix/Linux environments and scripting/programming languages such as Python, Tcl, and Shell.

• Experience building flow automation tools and integrating them into complex design pipelines.

• Ability to collaborate with cross-functional teams and translate user requirements into scalable solutions.

Preferred Qualifications:

• 10+ years of relevant industry experience with Design Automation tools

• Experience with Front End Pre-Silicon design verification flows

• Familiarity with advanced features of EDA tools like Lint/CDC/RDC etc.,

• Strong communication and collaboration skills, with the ability to partner across design and CAD/EDA teams.

• Prior experience in large-scale SoC or IP development environments.