Marvell Technology Logo

Marvell Technology

Digital Design Engineer

Posted 10 Days Ago
Be an Early Applicant
In-Office
Irvine, CA, USA
98K-144K Annually
Junior
In-Office
Irvine, CA, USA
98K-144K Annually
Junior
Design, verify and implement high-performance PHY and DSP ASIC blocks. Develop ASIC specs, architecture and RTL (Verilog/SystemVerilog). Create and execute verification plans, run lint/CDC/power analyses, optimize datapath designs, and collaborate with global teams.
The summary above was generated by AI

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Connectivity Group

What You Can Expect

  • Responsible for design, verification, implementation (ASIC) for high-performance, physical layer, high speed wired data communication networks.
  • Develop ASIC specification, architecture, and micro-architecture of major functional blocks in complex SOC solutions
  • Development/simulation of RTL hardware implementations in Verilog and System Verilog
  • Document and Execute verification plan
  • Analyze and improve design functionality with Lint, CDC and Power analysis
  • Participate and contribute in reviews
  • Work and communicate effectively with global team

What We're Looking For

  • 1-3 years plus experience in developing, implementing, and testing high performance communications and DSP ASIC products
  • Experience mapping communications algorithms to hardware and understanding of system design tradeoffs for high volume applications.
  • Must be familiar with signal processing circuit structure and architecture and high performance datapath DSP circuit design and optimization.
  • Must have extensive RTL experience including design, verification, and synthesis.
  • Must have strong UNIX-based EDA tool skills and in-depth knowledge of ASIC design flows.
  • Must be familiar with reusable HDL coding styles and design for high volume manufacture
  • Experience in bit-exact MATLAB and C/C++ based system simulation and evaluation a plus.
  • Familiarity with DSP and PHY layer communication protocols of 802.3 is a plus.

Expected Base Pay Range (USD)

97,700 - 144,410, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-JT2

Marvell Technology Irvine, California, USA Office

15485 Sand Canyon Avenue, Irvine, United States, 92618

Similar Jobs

3 Days Ago
In-Office
Senior level
Senior level
Hardware • Internet of Things
Design and architect digital subsystems for low-power IoT SoCs, implement RTL (SystemVerilog/Verilog), create testbenches and stimulus, manage multi-clock/power domains and timing closure, integrate security features (TrustZone, Secure Boot, PSA L2), and collaborate cross-functionally to deliver silicon to high-volume production.
Top Skills: AhbApbArm TrustzoneAxiEmbedded ProcessorsObiPsa Certified Level 2PythonSecure BootSoc ArchitectureStatic Timing AnalysisSystemverilogTclTiming ClosureUpfVerilog
9 Days Ago
In-Office
125K-235K Annually
Senior level
125K-235K Annually
Senior level
Aerospace • Logistics • Security • Software • Cybersecurity
Design, develop, modify, and evaluate high-speed digital circuitry for FPGA/ASIC systems. Implement FPGA hardware architectures and algorithms, collaborate with systems engineering, perform analysis, simulation and verification, select components, and support board/system debug and timing closure across the product lifecycle.
Top Skills: Amd/Xilinx FpgasAsicDspFpgaIntel/Altera Soc FpgasMatlabQuestasimSimulinkVhdlVivado
9 Days Ago
In-Office
114K-213K Annually
Senior level
114K-213K Annually
Senior level
Aerospace • Logistics • Security • Software • Cybersecurity
Design, develop, test, and support integrated analog/digital circuitry and electronic control systems for ship and submarine launch control. Responsibilities include analog and digital circuit design, PCB/layout and EMI/EMC troubleshooting, firmware development, data acquisition and cable design, lab testing, lifecycle support, and resolving field technical issues. Work autonomously on DoD programs requiring US citizenship and ability to obtain Secret clearance.
Top Skills: 10/100/1000Base-T EthernetCC#C++CanbusData Acquisition SystemsDmmEmi/EmcFccFpgasI2CIr TesterLabviewLabwindowsLtspiceMatlabMil-StdOscilloscopePcb LayoutPower IntegrityPspicePythonSignal IntegritySimulinkUart

What you need to know about the Los Angeles Tech Scene

Los Angeles is a global leader in entertainment, so it’s no surprise that many of the biggest players in streaming, digital media and game development call the city home. But the city boasts plenty of non-entertainment innovation as well, with tech companies spanning verticals like AI, fintech, e-commerce and biotech. With major universities like Caltech, UCLA, USC and the nearby UC Irvine, the city has a steady supply of top-flight tech and engineering talent — not counting the graduates flocking to Los Angeles from across the world to enjoy its beaches, culture and year-round temperate climate.

Key Facts About Los Angeles Tech

  • Number of Tech Workers: 375,800; 5.5% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Snap, Netflix, SpaceX, Disney, Google
  • Key Industries: Artificial intelligence, adtech, media, software, game development
  • Funding Landscape: $11.6 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Strong Ventures, Fifth Wall, Upfront Ventures, Mucker Capital, Kittyhawk Ventures
  • Research Centers and Universities: California Institute of Technology, UCLA, University of Southern California, UC Irvine, Pepperdine, California Institute for Immunology and Immunotherapy, Center for Quantum Science and Engineering

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account