Jobs at Marvell Technology

Lead test engineering for RF analog, mixed-signal, and silicon photonics products across silicon bring-up, qualification, characterization, and high-volume manufacturing. Own test software, equipment, PCBs, fixtures, probe hardware, and sockets; improve yield, test time, cost, coverage, and process robustness. Support customer returns, manage OSAT partners, coordinate global NPI development, and mentor engineers. Analyze wafer-sort data and communicate engineering findings to management.

Lead semiconductor product engineering for optics products from low- to high-volume manufacturing. Drive yield and cost improvements, production methods, quality, test coverage, guard bands, datasheet specifications, wafer-probe and package-level screening, RF test implementation, delivery coordination, customer return support, characterization, and qualification activities.

Accounting Intern supporting SEC financial reporting, technical accounting, general ledger close, global consolidations, journal entries, reconciliations, financial analyses, SEC filing schedules, 10-Q tie-outs, earnings releases, and SOX control documentation. The intern will use Oracle ERP, assist with accounting projects, and participate in process improvement and automation initiatives while gaining exposure to GAAP and corporate financial practices.

Leads development and qualification of advanced assembly technologies for silicon photonics and co-packaged optics products. Responsibilities include process development, characterization, DOE, process-window definition, supplier and OSAT collaboration, root-cause analysis, and resolution of assembly and reliability challenges. Provides technical leadership from technology evaluation through prototype builds and product qualification.

Leads Marvell’s regional Test Solutions Engineering team, owning ATE-based production test development, test architecture, validation, silicon characterization, NPI bring-up, and manufacturing ramp readiness. Provides technical leadership, mentors engineers, defines test strategies and specifications, optimizes test coverage and time, supports reliability qualification and failure analysis, and collaborates with design, DFT, product engineering, operations, quality, and hyperscale customers.

Support Storage Business Unit FP&A by building financial models, forecasting, and variance analysis. Drive new product investment planning, month-end accounting controls, project tracking, costing, dashboards, and cross-functional reporting. Partner with business leaders, support planning cycles, and mentor junior team members to deliver actionable financial insights.

Leads Marvell’s IT SOX compliance program, including risk assessment, scoping, ITGC and ITAC testing, control documentation, audit coordination, remediation, training, and process improvement. The role supports technology implementations and partners with IT, internal audit, external audit, and business leaders. Candidates need 8+ years of IT SOX or IT audit experience, Oracle EBS expertise, and proficiency with audit platforms such as AuditBoard or Fastpath.

Design and validate high-performance broadband analog and mixed-signal circuits for optical and electrical receiver and transmitter chips. Responsibilities include developing CMOS and BiCMOS circuits, analog front ends, TIAs, drivers, regulators, sensors, and related circuitry; supporting tapeout, laboratory evaluation, post-silicon validation, qualification, production transition, and customer support.

Leads a team designing and validating high-speed broadband analog and mixed-signal ICs, including optical TIAs and modulator drivers using SiGe BiCMOS and FinFET technologies. Responsibilities include architecture, technical leadership, multidisciplinary collaboration, chip development through mass production, post-silicon validation, methodology development, performance management, mentoring, customer support, and ensuring timely, high-quality deliverables.

Lead test strategy, DFT architecture, test-chip validation, silicon bring-up, mixed-signal characterization, and manufacturing test planning for advanced SerDes, chiplet, and die-to-die semiconductor products. Partner with design, validation, product engineering, reliability, and manufacturing teams to improve testability, diagnostics, quality, yield, and production readiness. Mentor engineers and lead complex cross-functional technical initiatives.

Supports analog IC physical layout by translating schematics into Cadence Virtuoso layouts, running DRC and LVS verification, collaborating with analog designers, debugging designs, and contributing to semiconductor IP tapeouts on advanced process nodes.

Leads Marvell’s global test hardware engineering organization across ATE load boards, probe cards, sockets, and handler change kits. Oversees hardware strategy, design, supplier management, NPI, production support, capacity planning, budgets, and technology qualification. Builds and manages a worldwide team, partners with Test, Product, Design Engineering, and Supply Chain, and drives first-time-right hardware designs through manufacturing ramp. Requires semiconductor test hardware expertise, SI/PI knowledge, thermal and mechanical engineering oversight, and extensive leadership experience.

Supports digital IC design and implementation for high-performance semiconductor products. Develops and verifies RTL blocks, performs synthesis, static timing and power analysis, debugs designs, explores design methodologies, and collaborates with architecture, verification, and physical design teams. The intern contributes to real chip design efforts involving cloud, AI, storage, networking, and high-speed connectivity applications.

Design and verify high-performance RTL blocks for digital ICs, including synthesis, static timing analysis, timing signoff, power analysis, and debugging. Interns collaborate with architecture, design verification, and physical design teams on ASIC and SoC projects, investigate design methodologies, and contribute to real semiconductor products for cloud, AI, storage, and networking applications.

Lead digital ASIC design for high-performance connectivity silicon supporting AI data centers. Responsibilities include SoC microarchitecture, SystemVerilog RTL development, ASIC front-end flows, timing and power optimization, subsystem integration, verification strategy, emulation, FPGA prototyping, and silicon bring-up. The role focuses on DSP pipelines, high-speed datapaths, Ethernet protocols, PHY logic, and advanced process nodes while mentoring engineers and driving technical direction.

Leads end-to-end execution of customer-driven custom and semi-custom semiconductor programs, from initiation and planning through development, validation, qualification, sample delivery, production release, and closure. Manages schedule, quality, cost, risks, communications, and issue resolution across matrixed engineering, operations, business, customer, and executive stakeholders. Drives alignment, mitigation planning, post-mortems, and continuous improvement.

Develop and optimize semiconductor test programs for the Advantest 93K platform, including characterization, production, wafer sort, high-speed testing, pattern conversion, and test flow improvement. Collaborate with design, DFT/DFM, and product engineering teams to improve yield, reduce test time, document methodologies, and release production test programs.

Develops and optimizes semiconductor test solutions for Custom ASIC, network switch, and processor products. Responsibilities include creating characterization, production, wafer-sort, and high-speed test programs on Advantest 93K or Teradyne platforms; designing tester hardware; converting test patterns; improving yield and test time; conducting testability reviews; and releasing production programs. Collaborates with product, hardware, design, systems, firmware, DFT, and DFM teams.

Develop and test embedded software, kernel PHY drivers, APIs, utilities, diagnostics tools, and automated test infrastructure for Ethernet transceivers. Build Python-based GUI and data analysis systems, collaborate with hardware and firmware teams on performance optimization, and support field application engineers with customer issues. The role requires strong C and Python skills, embedded systems experience across Linux and Windows, debugging expertise, and familiarity with Ethernet protocols and development workflows.

Leads semiconductor product qualification and reliability testing, including strategy, planning, qualification hardware, stress testing, supplier coordination, failure analysis, and technical reporting. Collaborates with cross-functional teams, testing laboratories, and vendors to qualify new products, processes, materials, and manufacturing changes. Supports customer quality requirements and applies semiconductor reliability standards, statistical analysis, and risk assessment methods.