Develop and maintain SystemVerilog/UVM testbenches, UVCs, automated tests, and C-based hardware/software integration tests for FPGA verification. Create test plans, analyze functional and code coverage, drive coverage closure, debug failures, and collaborate with design, architecture, and firmware teams from planning through tape-out. Own verification deliverables, communicate risks, participate in technical reviews, and mentor junior engineers.
- FPGA Design Verification Engineer
- Client-Boeing
- IP layer- VDart
- Location: El Segundo, CA, onsite five days per week
- Employment Type: W-2 Contract
- Duration: 12 months
- Compensation:$70 per hour
- Work Authorization: U.S. citizenship required
- Experience: 5+ years in FPGA Design Verification
- Clearance: DoD Secret clearance preferred
Job Description:
Key Skills:
- FPGA Design Verification
- SystemVerilog and UVM testbench development
- C test development and hardware/software integration
- Test plan development, functional coverage, and coverage closure
- Universal Verification Component (UVC) development
- FPGA verification from test planning through tape-out
Responsibilities
- Develop and maintain SystemVerilog/UVM testbenches, reusable Universal Verification Components (UVCs), and automated tests.
- Create verification plans covering FPGA functionality, interfaces, and hardware/software interactions.
- Develop and integrate C-based tests, APIs, and software build flows.
- Implement mailbox mechanisms and communication components supporting hardware/software verification.
- Collect and analyze functional and code coverage, identify gaps, and drive coverage closure.
- Debug test failures, document defects, and collaborate with design and firmware engineers to resolve issues.
- Work with verification, architecture, design, and firmware teams to define verification scope and review results.
- Improve verification environments to increase defect detection and test efficiency.
- Own verification deliverables, communicate risks, and escalate issues when appropriate.
- Mentor junior engineers and participate in technical reviews.
Preferred Skills:
- SpaceWire Protocol
- DDR4 Memory Interfaces
- SerDes Connectivity
- Configuration, Control, and Telemetry Systems
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