ASIC Design Engineer

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

As an ASIC Design Engineer at Ciena, you will be a pivotal force in the development of high-performance ASICs that are integral to our cutting-edge networking solutions. Under the direction of the Director of ASIC Engineering, your role involves a critical blend of innovation and precision. You will define, design, and implement complex digital blocks, ensuring the creation of innovative and reliable hardware that propels Ciena's market leadership.

How You Will Contribute:

• Define comprehensive block-level design documents, including interface protocols, block diagrams, and transaction flows, ensuring alignment with system requirements.
• Perform RTL coding and engage in function/performance simulation, debugging, and various checks (Lint, CDC, FV, UPF) to maintain high design standards.
• Participate in synthesis, timing and power closure, and the bring-up of FPGA/silicon, collaborating closely with cross-functional teams to meet project timelines.
• Develop and execute detailed test plans and coverage analysis for block and SOC-level verification, enhancing the reliability and performance of our products.
• Develop test benches and tests for FPGAs and ASICs.

The Must Haves:

• Bachelor of Science degree in Electrical Engineering coupled with proven experience ASIC development with Verilog.
• Experience with ASIC design verification, synthesis, timing/power analysis and DFT.
• Experience with modern SoC design architectures.
• ARM/MIPS type processor cores.
• Strong debug and lab experience.

Assets:

• Master of Science or PhD in Electrical Engineering.
• Knowledge of high performance and low power design techniques.
• Experience with Ethernet, Networking, and Data Communications
• Knowledge of FPGA and emulation platforms.
• Knowledge of SOC architecture
• Develop diagnostic software for FPGAs

Pay Range:

The annual salary range for this position in California is $130,900 - $209,100.

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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.  Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.