Jobs at Tenstorrent Inc.

Design and implement chip-level DFT strategies for high-speed CPU cores and multi-chiplet SiP. Implement and verify scan chains, memory BIST, and JTAG. Partner with RTL, physical design, and verification teams. Script and automate DFT flows using EDA tools (ATPG, fault coverage) and support SoC-level silicon debug, formal verification, and DFT signoff.

Contract recruiter responsible for full-cycle hiring for supply chain, procurement, manufacturing operations, logistics, supplier quality, planning, and business operations. Build talent pipelines beyond LinkedIn, partner with hiring managers to scope roles and move searches, assess and close candidates, and maintain process-oriented, scalable recruiting workflows. 6-month contract, remote with location preferences.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.

Build and maintain infrastructure automation, integrations, and SRE tooling. Develop backend services, infrastructure-as-code, observability, and provisioning for bare metal, VMs, and Kubernetes. Collaborate with hardware, software, and AI teams, drive operational excellence, and provide technical leadership.

Lead and grow a software engineering team focused on RISC-V software ecosystem, collaborating with teams to establish RISC-V as the standard.

Run deal governance, escalation management, and cross-functional coordination to remove blockers and accelerate sales execution. Partner with Sales, Legal, Finance, Trade Compliance, and Operations to manage deal logistics, contract review, forecast support, S&OP, incentive reconciliation, and CRM-driven processes to scale GTM operations.

Lead architecture and microarchitecture of RISC-V CPU vector, floating-point, and matrix extensions. Translate HPC/AI workload needs into scalable CPU designs, optimize performance/power/area, define architectural specs, lead cross-functional teams from concept through silicon, and work on RTL development to enable efficient heterogeneous compute for AI/HPC.

The Performance Architect will work on high-performance systems with expertise in software and hardware, focusing on AI and HPC solutions.

As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.

Own Tenstorrent's developer platform including firmware, system software, packaging, updates, and a unified CLI. Define roadmap, prioritize engineering work, partner with DevRel and customers, ship iterative improvements, and measure success via developer NPS and CLI adoption.

Design and implement full‑custom analog/mixed‑signal layouts for high‑performance IP in advanced FinFET nodes. Translate schematics to manufacturable layouts, optimize floorplans for PPA and matching, run and close physical verification (DRC/LVS/ERC/DFM/antenna), perform post‑layout extraction/simulation, and integrate blocks into SoCs. Develop layout automation and collaborate with circuit designers to meet performance, noise, and reliability targets.

Build and operate AI inference deployments, write production code, debug full inference stack, collaborate with customers and engineering, and drive performance/observability improvements using Kubernetes, Helm, and LLM serving tools.

Lead as a hybrid Chief of Staff and execution-focused TPM for the RISC-V software org: define goals, plan and track execution, manage dependencies and risks, drive cross-functional initiatives, support headcount and recruiting, prepare leadership materials, and represent the team to partners and customers.

Define and own chiplet-based compute platform architectures for high-performance RISC-V CPUs in SiP solutions. Lead design of PCIe, die-to-die connectivity, coherent fabrics, system management, and confidential computing subsystems. Collaborate with architecture, hardware, software, and external IP partners to deliver production-ready chiplet architectures and drive cross-functional execution.

Design board-level routing studies, mock-ups, and SI/PI modeling to support early-stage semiconductor package and package-board co-design. Collaborate with signal integrity, power integrity, mechanical, and system teams to develop PCB routing environments for BGA optimization, package escape studies, and system-level electrical modeling. Apply engineering judgment to evaluate tradeoffs and improve workflows using automation and data analytics.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.

Build and run an enterprise sales motion for AI hardware and software: own accounts through the full lifecycle, align technical solutions to business value, collaborate cross-functionally, develop repeatable processes and materials, and manage long, complex procurement cycles to accelerate revenue.

Lead hardware-software co-design to enable AI/HPC and agentic AI stacks on RISC-V CPUs. Integrate and optimize low-level kernel infrastructure, runtimes, distributed execution, memory systems, and developer tools, collaborating with architects, compiler engineers, and kernel developers to meet performance targets.

Lead and enhance global People Operations, focusing on employee lifecycle management, operational excellence, and compliance across multiple regions.