Teams at SiFive

Leads functional safety and reliability work for processor and SoC platforms across automotive, robotics, AI, and data center applications. Owns safety requirements, goals, traceability, risk analysis, verification, assessments, audits, certification, and customer support. Applies ISO 26262, FMEDA, fault modeling, diagnostic coverage, safety cases, and fault injection. Coordinates architecture, design, verification, software, quality, product, program management, and customer-facing teams while addressing RAS mechanisms and technical risks.

Own formal verification for high-performance out-of-order RISC-V CPU cores, including planning, assertions, proof strategies, abstraction, debugging, and signoff closure. Develop scalable formal environments and infrastructure for control, ordering, pipeline, load-store, clock-gating, and microarchitectural behavior. Analyze failures and coverage gaps, collaborate with architecture and RTL teams, improve verification methodology, and mentor engineers.

Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.