Jobs at NVIDIA

Lead a data science team to design, build, and deploy large-scale, real-time AI/ML solutions (forecasting, diagnostics, LLM chatbot, retention models, optimization) to optimize GPU cloud gaming performance and user experience.

Lead technical program planning and execution for key partners, translating customer requirements into cross-functional tasks, driving global program delivery from design through production, managing issues/bugs and post-deployment support, and communicating program health and risks to customers and leadership to ensure on-time, high-quality outcomes.

The Senior Localization Engineer will build robust localization solutions using navigation maps for autonomous vehicles, ensuring real-time performance and adherence to automotive safety standards.

Develop and enhance the NIM Platform SDK and microservice framework, focusing on high-performance AI inference. Collaborate across teams and optimize cloud microservices for scalability and reliability.

Design hardware accelerators and processors, develop power metrics, and collaborate with teams to deliver efficient, high-performance RTL.

Develop and design innovative circuits in deep submicron technologies, collaborate with teams for performance improvements, mentor junior members, and prototype ideas on test chips.

Lead ASPICE and HW SPICE assessments, mentor teams, and communicate findings to enhance process maturity in automotive programs. Requires strong ASPICE knowledge and program management experience.

Develop AI systems for efficient inference, design and optimize kernels, and build domain-specific compilers and runtimes while collaborating with engineers.

Design and implement compiler optimizations and infrastructure for deep learning inference. Analyze networks, improve performance and memory, define public APIs, collaborate with framework and hardware teams, and deliver ahead-of-time and just-in-time compilation solutions.

Lead full-flow physical implementation for LPU ASICs: synthesis, floorplanning, place & route, timing closure, UPF/LEC low-power flows, and tapeout. Collaborate with IP, front-end, PnR and sign-off teams to optimize PPA and resolve bottlenecks. Architect automated, data-driven EDA methodologies, implement scripts and AI-assisted optimizations, and ensure sign-off quality including power grid, EMIR, and DFT integration for high-speed SerDes blocks.

Design, build, and operationalize large-scale AI and HPC hybrid compute solutions for partners. Guide adoption of NVIDIA compute, networking, and software stacks, deliver demos and POCs, troubleshoot cluster, network, and storage issues, and collaborate with engineering and executives to deploy AI factories at scale.

Design and build agentic workflows that automate code generation, testing, and tuning across NVIDIA frameworks and compilers. Partner with internal engineering teams to identify high-impact automation, iterate on proofs of concept, integrate agents into git-native CI pipelines, and enable closed-loop validation on real GPUs. Contribute to multi-agent orchestration, performance optimization, and reusable internal tooling to scale agentic engineering practices.

Design and build real-time, physics-informed AI models and synthetic data pipelines for quantum calibration and decoding. Develop surrogate models and GPU-accelerated implementations, apply reinforcement and online learning for calibration policies, co-design low-latency calibration-decoding systems, and collaborate across engineering and research to enable fault-tolerant quantum hardware.

The role involves defining verification strategies, building infrastructure for SoC verification, and collaborating with various teams to meet project requirements.

Lead research and development of high‑fidelity, physics‑based quantum device models, noise models, and synthetic data pipelines. Build GPU‑accelerated simulation frameworks, validate models against experiments, and collaborate with product, engineering, and research teams to enable fault‑tolerant quantum hardware simulation and real‑time modeling.

The role involves validating clocking structures in products, developing test plans, automation, and partnering with design teams to ensure high-quality verification of ASIC designs.

Design, implement, and extend compute debugger tools and libraries for NVIDIA GPUs across Windows, Linux, and embedded RTOS. Apply debugger, binary-instrumentation, and computer-architecture expertise to integrate new features, collaborate with cross-functional teams, document designs, estimate work, perform peer reviews, and mentor junior engineers.

The Senior Formal Verification Engineer will verify sophisticated ASIC builds using formal methods, collaborate with architecture teams, develop verification environments, and support silicon debug.

As a Senior DFT Engineer, you'll develop DFT architecture for AI Chips, collaborating on DFT methodologies and ensuring product quality.

Design, deploy, and operate Kubernetes-based large-scale storage and data platforms. Build automation, tooling, telemetry, and observability. Troubleshoot distributed systems, support CI/CD and IaC, participate in on-call rotations, capacity planning, and launch readiness.