Jobs at NVIDIA

Lead developer relations with US national labs and federal research: build strategic collaborations, embed NVIDIA quantum SDKs, run workshops and trainings, present at conferences, create reference implementations, and relay research needs to product and engineering teams to drive adoption of CUDA-Q, cuQuantum, CUDA-Q QEC, and NVQLink.

Build, scale, and harden deep learning training infrastructure for multi-thousand GPU clusters. Improve data loaders, distributed training, scheduling, and performance monitoring. Develop fault-resilient orchestration, training pipelines for massive video datasets, and collaborate with researchers and platform teams to maximize training efficiency, availability, and scalability.

Own strategy and execution for a portfolio of AI-native and hyperscale customers. Serve as primary relationship owner, drive revenue, market share and product adoption, coordinate with solution architects, product marketing, OEMs and partners, forecast and train customers, and evangelize NVIDIA platforms to accelerate enterprise growth.

Lead planning and execution for GPU-accelerated data science and processing libraries. Drive cross-functional release and compliance programs, manage dependencies and risks, improve dev processes and tooling, build program metrics, and ensure high-quality, predictable open-source releases.

Design, build, and maintain scalable infrastructure and CI/CD pipelines for TensorRT Edge-LLM across embedded and desktop GPU/CPU platforms. Configure and operate tools (CMake, GitLab, GitHub Actions, Kubernetes, Docker), monitor systems, automate builds/tests, address security CVEs, and collaborate with autonomy and external partners to improve development velocity and reliability.

Design and optimize high-speed, high-density ASIC package layouts and substrate breakouts. Perform pinout optimization, routing, placement, stack-up, power distribution, CAD library development, feasibility studies, and productivity methodology improvements while collaborating with package leads and cross-functional teams.

Design and perform physical layout for silicon interposers using Cadence Virtuoso; run DRC/LVS and verification (Calibre, ICV, Thunder); perform feasibility studies, floorplanning, custom layout, and collaborate with package, SI, and technology teams to meet schedule, cost, manufacturability, and electrical goals.

Lead design and development of infrastructure, automation frameworks, and internal developer tools. Build scalable services, APIs, dashboards, workflow engines, and LLM-powered workflows integrated with CI/CD, source control, test infrastructure, and observability. Define architecture and reliability practices, mentor engineers, review designs, and provide technical leadership for automation and tooling projects.

Optimize large-scale AI inference performance by designing reproducible experiments, profiling GPU workloads, tuning serving configurations (batching, KV cache, quantization, parallelism), and delivering fixes upstream (framework patches, kernels, deployment recipes) across TensorRT-LLM, vLLM, SGLang and related stacks.

Lead HBM and LPDDR system integration and bringup for next-generation SoCs. Own memory performance, power, thermal, and reliability closure across silicon, package, board, and firmware. Drive post-silicon margining, VF shmoo, eye characterization, and correlation. Debug training, calibration, SI/PI, and system stability issues. Define validation, characterization, and issue-tracking plans to produce production-ready operating points.

Lead technical customer engagements to design, build, and deploy GPU-accelerated AI/ML, DL, and data analytics solutions on cloud platforms. Create PoCs, run demos, collaborate with sales and engineering, deliver workshops and technical presentations, and troubleshoot customer deployments at scale.

Research and implement GPU-acceleration techniques for high-performance databases and ETL. Analyze and optimize data-intensive workloads, collaborate with hardware, systems, and research teams to influence next-generation architectures and programming models, and publish/share findings with customers and the community.

Research and develop techniques to accelerate large-scale applications on advanced CPU platforms. Analyze and optimize database and analytics workloads for CPU performance, collaborate with internal and external experts, publish findings, and influence next-generation hardware/software design.

Lead a team of performance engineers to optimize complex workloads on NVIDIA's CPUs and GPUs, driving technical excellence and innovation while mentoring team members and collaborating with cross-functional partners.

The Senior Developer Technology Engineer will optimize GPU applications in the public sector by collaborating with developers, crafting parallel algorithms, and improving software stacks while ensuring high performance on GPUs.

Research and develop GPU-accelerated techniques for AI and financial workloads. Analyze and optimize performance on CPU/GPU architectures, collaborate with industry and academia, publish findings, and influence hardware and software design while supporting developer adoption.

As a Senior Software Architect for AI Networking, you'll design and implement AI networking technologies, optimize data processing in AI systems, and collaborate on cutting-edge solutions.

Develop AI compiler solutions, optimize GPU programming, build training pipelines, collaborate on integrating AI policies, and conduct rigorous performance benchmarking.

Manage a team developing accelerated image and data compression libraries. Define project goals, roadmap, and scope; ensure execution and delivery; elevate engineering practices; collaborate with internal and external customers and the open-source community while fostering an inclusive, innovative environment.

This role involves researching and optimizing applications for NVIDIA's computing platform, collaborating with customers and internal teams to enhance performance and design next-generation software and hardware.