Teams at Baya Systems

Own RTL-to-GDS physical implementation for high-performance SoC and chiplet designs, including synthesis, floorplanning, placement and routing, clock tree synthesis, timing and power closure, EM/IR analysis, physical design validation, DRC, LVS, and final signoff. Collaborate with microarchitects on performance, power, and area trade-offs, conduct feasibility studies, and develop physical design methodologies and automation recipes.