Microchip Technology Inc. Logo

Microchip Technology Inc.

Senior Technical Staff Engineer - Design (IO Lead Design-FPGA)

Posted 16 Days Ago
Be an Early Applicant
In-Office
San Jose, CA
88K-232K Annually
Senior level
In-Office
San Jose, CA
88K-232K Annually
Senior level
The role involves technical leadership in analog circuitry design and verification for FPGA I/Os, collaborating with architecture, layout, and ASIC teams, and mentoring junior engineers.
The summary above was generated by AI

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Microchip Technology Inc. has a Senior Technical Staff Engineer - IO Design Lead opening based in San Jose, California. This engineer will be responsible for providing technical leadership in the architecture definition, design, modeling, integration, and verification of complex analog circuitry (clocking, Rx, Tx) integrated into the IO’s of the FPGA.

  • Develop analog circuits for GPIO, HSIO, high-speed DDR and other IO applications in advanced FinFET nodes.

  • Work with architecture team to understand chip requirements and translate them into circuit architectures and implement and simulate them.

  • Contribute to the micro architecture and circuit design, simulation and optimization of various IO blocks such as clocking (PI, DLL, PLL), CTLE, VGA, Tx.

  • Collaborate with layout and ASIC PnR team to optimize IO floorplan, placement and routing of power and critical signals.

  • Develop IO system models to determine system budgets, identify performance bottlenecks and create implementable design specs.

  • Drive analog and digital design, AMS verification, layout across different geographies and time zones.

  • Improve current and develop new calibration and training algorithms of various sub-blocks in the IO’s to meet high-speed performance.

  • Work with the ESD engineer to integrate the ESD design into IO blocks.

  • Layout guidance and mentorship of junior engineers.

  • Work with the layout lead in planning the distribution of critical signals and clocks, placement of IO blocks, and design of the IO power distribution network.

  • Propose new mixed-signal flows for IO designs that will enhance the efficiency and quality of current and future designs

  • Investigate new architectures and circuit design techniques for current and future generations of FPGA IO’s.

  • Support IO Mixed-Signal IP through post-tapeout phase, including lab testing, customer bring-up and debug.

Requirements/Qualifications:

  • Bachelors and/or Master’s in Electrical Engineering, Physics, Computer Engineering or Computer Science preferred.

  • 15+ years of proven silicon experience in design and verification of high-speed IOs and verification efforts in multiple technology nodes.

  • System modeling of IO’s using Matlab and System C/System Verilog.

  • Familiarity with FinFet technology. Knowledge go industry standard tools like Spice, Virtuoso, AMS/Co-sim, Matlab.

  • Competency in HSPICE, co-sim, and testbench generation and simulation.

  • Knowledge about high speed design techniques (DDRx, PCI-e, USB, MIPI) and calibrations.

  • Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel.

  • Knowledge of power analysis.

  • Good analytical, oral and written communication skills

  • Able to write clean, readable presentations.

  • Self-motivated, proactive team player.

  • Ability to work to schedule requirements.

Travel Time:

0% - 25%

Physical Attributes:

Feeling, Handling, Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

15% standing, 15% walking, 70% sitting; 100% In doors; Usual business hours

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Top Skills

Ams
Fpga
Hspice
Matlab
Spice
System C
System Verilog
Virtuoso

Microchip Technology Inc. Irvine, California, USA Office

Irvine, CA, United States

Similar Jobs

3 Hours Ago
Remote or Hybrid
Santa Clara, CA, USA
159K-278K Annually
Senior level
159K-278K Annually
Senior level
Artificial Intelligence • Cloud • HR Tech • Information Technology • Productivity • Software • Automation
As a Staff DevOps Engineer, you will support, deploy, and maintain Big Data infrastructure, manage containerized applications, automate CI/CD pipelines, and collaborate with various teams to resolve issues in a 24x7 production environment.
Top Skills: AnsibleBashBig DataCloudera Data PlatformDockerFlinkGitGrafanaHadoopHbaseHdfsHiveImpalaJenkinsKafkaKubernetesKuduMariadbPostgresPrometheusPythonRabbitMQRedisSparkSQLVictoriametricsYarn
3 Hours Ago
Remote or Hybrid
Santa Clara, CA, USA
125K-213K Annually
Senior level
125K-213K Annually
Senior level
Artificial Intelligence • Cloud • HR Tech • Information Technology • Productivity • Software • Automation
The Senior Network Operations Engineer operates and maintains cloud network infrastructure, resolves network issues, and drives automation for deployment across large-scale environments. Responsibilities include monitoring, troubleshooting, and collaborating with various teams to enhance network performance and reliability.
Top Skills: AnsibleAWSAzureBashDockerF5GCPGitlabGrafanaKubernetesLinuxNginxPrometheusPythonSplunkTerraform
5 Hours Ago
In-Office
San Francisco, CA, USA
90K-120K Annually
Senior level
90K-120K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Machine Learning • Other • Software • Infrastructure as a Service (IaaS)
As a Technical Support Engineer, you'll manage incidents, communicate with customers, improve responses, and ensure system reliability, leveraging your technical skills and experience.
Top Skills: Ai/Ml InfrastructureBashJavaScriptKubernetesLinuxPythonSlurm

What you need to know about the Los Angeles Tech Scene

Los Angeles is a global leader in entertainment, so it’s no surprise that many of the biggest players in streaming, digital media and game development call the city home. But the city boasts plenty of non-entertainment innovation as well, with tech companies spanning verticals like AI, fintech, e-commerce and biotech. With major universities like Caltech, UCLA, USC and the nearby UC Irvine, the city has a steady supply of top-flight tech and engineering talent — not counting the graduates flocking to Los Angeles from across the world to enjoy its beaches, culture and year-round temperate climate.

Key Facts About Los Angeles Tech

  • Number of Tech Workers: 375,800; 5.5% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Snap, Netflix, SpaceX, Disney, Google
  • Key Industries: Artificial intelligence, adtech, media, software, game development
  • Funding Landscape: $11.6 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Strong Ventures, Fifth Wall, Upfront Ventures, Mucker Capital, Kittyhawk Ventures
  • Research Centers and Universities: California Institute of Technology, UCLA, University of Southern California, UC Irvine, Pepperdine, California Institute for Immunology and Immunotherapy, Center for Quantum Science and Engineering

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account