Astera Labs Logo

Astera Labs

Principal Physical Design Engineer (STA)

Posted 19 Days Ago
Be an Early Applicant
In-Office
San Jose, CA
209K-250K
Senior level
In-Office
San Jose, CA
209K-250K
Senior level
Drive planning, coordination, and execution in the design of ASICs for connectivity products, collaborating across teams for successful delivery.
The summary above was generated by AI

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. 

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.

Basic Qualifications:

  • Strong academic and technical background in electrical engineering. A bachelor's degree in EE / Computer Science is required, and a master's degree is preferred.
  • ≥12 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. 
  • Entrepreneurial, open-minded behavior and a can-do attitude. Think and act fast with the customer in mind!

Required Experience:

  • Proven expertise in developing/maintaining timing constraints, timing signoff methodology, and timing closure at the block and full-chip level.
  • Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
  • Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
  • Experience with Cadence and/or Synopsys physical design tools/flows.
  • Familiarity and working knowledge of System Verilog/Verilog.
  • Experience with DFT tools and techniques.
  • Experience in working with IP vendors for both RTL and hard-macro blocks.
  • Good scripting skills in tcl, python, or Perl.

Preferred Experience:

  • Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
  • Familiarity with DFT test coverage and debug.
  • Familiarity with ECO methodologies and tools.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Top Skills

Cadence
Perl
Python
Synopsys
System Verilog
Tcl
Verilog

Similar Jobs

An Hour Ago
Hybrid
San Francisco, CA, USA
Expert/Leader
Expert/Leader
Financial Services
As a Commercial Banker, you'll focus on acquiring new clients and maintaining strong relationships within the Mid-Corporate Banking sector, emphasizing strategic financial advice and innovation.
An Hour Ago
Hybrid
San Francisco, CA, USA
Junior
Junior
Financial Services
Support Client Advisors in Private Banking with client information management, preparation of banking product pitches, account administration, and trade execution.
Top Skills: ExcelPowerPoint
An Hour Ago
Hybrid
San Francisco, CA, USA
Mid level
Mid level
Financial Services
Provide support to Client Advisors in managing relationships, conduct account administration, and assist with documentation and reporting. Coordinate with multiple teams and monitor client accounts.
Top Skills: ExcelPowerPoint

What you need to know about the Los Angeles Tech Scene

Los Angeles is a global leader in entertainment, so it’s no surprise that many of the biggest players in streaming, digital media and game development call the city home. But the city boasts plenty of non-entertainment innovation as well, with tech companies spanning verticals like AI, fintech, e-commerce and biotech. With major universities like Caltech, UCLA, USC and the nearby UC Irvine, the city has a steady supply of top-flight tech and engineering talent — not counting the graduates flocking to Los Angeles from across the world to enjoy its beaches, culture and year-round temperate climate.

Key Facts About Los Angeles Tech

  • Number of Tech Workers: 375,800; 5.5% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Snap, Netflix, SpaceX, Disney, Google
  • Key Industries: Artificial intelligence, adtech, media, software, game development
  • Funding Landscape: $11.6 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Strong Ventures, Fifth Wall, Upfront Ventures, Mucker Capital, Kittyhawk Ventures
  • Research Centers and Universities: California Institute of Technology, UCLA, University of Southern California, UC Irvine, Pepperdine, California Institute for Immunology and Immunotherapy, Center for Quantum Science and Engineering

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account