Principal FPGA / RTL Design Engineer - Signal Processing

THE OPPORTUNITY

Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who will report to the Senior Engineering Director in Irvine and work closely with the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.  FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D.  These are exciting projects aimed at addressing challenging real-world communication needs. 

This Principal FPGA / RTL Design Engineer is 100% onsite, Monday through Friday, at Silvus Technologies’ Engineering and R&D Office in Irvine, CA, near the vibrant Irvine Spectrum.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

• Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting; familiarity with logic analyzers.
• Provide support to the RF and Software Engineering teams.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
• Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields.
• Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs.
• Deep knowledge of RTL design fundamentals using Verilog and System-Verilog.
• Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
• Must be a U.S. Citizen due to clients under U.S. government contracts.
• All employment is contingent upon the successful clearance of a background check and drug testing..

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• MS. or Ph.D. degree in Electrical Engineering, Computer Science, or relevant fields.
• Basic MATLAB skills.
• Solid knowledge and understanding of scripting languages such as Perl and Python.
• Strong communication and presentation skills.
• Experience with wireless communication systems on FPGA or ASIC designs.

WORKING CONDITIONS & PHYSICAL REQUIREMENTS

• Office environment.
• Occasional exposure to heat, cold, and allergens while performing tests or demonstrations in the field.
• While performing the duties of this job, the employee is required to do the following:
  • Lift equipment up to 20 lbs. for the set-up of demonstrations and testing.
  • Perform bending and reaching movements to place items on lower and higher shelves.
  • Kneeling or squatting to access lower shelves.
  • Walking/Moving in the labs