Principal Engineer, IP Design Verification

Lead and Performs functional logic verification of complex IP cores used in our FPGA products and to ensure design will meet specification requirements. Develops FPGA IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, , and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques like emulation and formal used to enable feature coverage as per the microarchitecture specifications.

Minimum Qualifications

• BS in Electrical Engineering, Computer Science or related field

• 10+ years of experience in design verification at the IP and subsystem levels.

• Demonstrated knowledge of System Verilog, UVM, Use of formal and emulation a plus.

• Demonstrated understanding of digital design, protocols and silicon architectures.

• Proven experience in leading various aspects of IP/subsystem verification etc