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Intel

Lead Customer Support Engineer - Memory

Reposted 9 Days Ago
Be an Early Applicant
4 Locations
186K-263K Annually
Senior level
4 Locations
186K-263K Annually
Senior level
The Lead Customer Support Engineer resolves customer issues related to Memory design, manages interactions with R&D, develops documentation, and contributes to customer support and training efforts.
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Job Details:

Job Description: 

The Lead Customer Support Engineer will be supporting internal and external customers of Intel Foundry, focusing on Memory Compilers, Custom Embedded Memories, and eFUSE.

The responsibilities will include:

  • Timely resolution of customer issues related to Memory functionality, Memory timings and Memory usage in SOC's
  • Replication, debug of issues either individually or through experts and managing interactions with customers and IP developers to fully understand the issue, provide work arounds and solutions.
  • Developing great working relationships with customers and RnD teams.
  • Understanding of the competitive landscape and proactive identification of gaps in the FIP offering and proposing solutions to address such gaps. Helping customers boost productivity.
  • Identification, prioritization of customer requirements and collaboration with Customer Account Management and RnD functions on developing FIP roadmap and delivering solutions.
  • Proactive contribution to customer facing and internal documentation and technical training materials.
  • Developing technical presentations, app notes and assisting customers in FIP evaluation.
  • Influencing RnD and QA team on ensuring continuous improvement of FIP collateral quality.

Qualifications:

You must possess the minimum qualifications listed below to be considered for this position. Preferred qualifications are not required, but all other things being equal they will give you an advantage in the interview process.

Minimum Qualifications:

  • Bachelor’s degree in electrical engineering, computer science or similar engineering field with 10+ years or a Master’s degree and 8+ years of Memory design experience
  • Experience working on at least some of the different types of memories (SRAM/ROM/RF/TCAM, eFuse, antiFuse).
  • Experience hands on working in all aspects of memory design (circuit design, layout, characterization, views generation, views use, QA) is a must.
  • The role would require the person to have in depth working knowledge of different memory architectures and all memory views (gds, oasis, spice, lef, cdl, lib, verilog, atpg, pgv, apl, ndm, mtv, etc.)
  • Understands memory integration in SOC and how views are consumed in EDA flows
  • Understanding of SoC design utilizing at least one industry standard EDA tool stack (Synopsys, Cadence, Siemens EDA).
  • Experience with physical, timing and reliability sign off, including hands on experience is resolving related issues in design.
  • Experience presenting to customers and upper management.
  • Experience debugging design and EDA workflow issues, combined with experience prioritizing based on deep understanding of the impact on customers.
  • Hands on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and antiFUSE.
  • Scripting skills, preferably in TCL and Python.

Preferred Qualifications:

  • Team leadership experience
  • Experience with project management best practices.
  • Experience using Jira Service Management and Jira Software platforms.
  • Experience prioritizing and dispositioning multiple streams of issues and customers.
  • Experience with design and sign off on advanced process nodes.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:US, California, Folsom, US, California, Santa Clara, US, Texas, Austin

Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Top Skills

Cadence
Python
Siemens Eda
Synopsys
Tcl

Intel Irvine, California, USA Office

111 Theory, Irvine, CA, United States, 92617

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