PCI Express Chiplet Architect

Tenstorrent is looking for an experienced PCI Express Chiplet Architect to define and lead the architecture of future IO chiplets that integrate high-performance RISC-V CPUs and AI accelerators. You’ll work across teams to build robust, scalable chiplet specifications that bridge protocol domains, interconnect technologies, and system software requirements. This is a strategic and highly cross-functional role—ideal for someone who enjoys solving complex architectural problems and aligning diverse teams on technical direction.The role is open to candidates with strong IO, interconnect, and system integration experience

This role is remote, based out of the United States or Canada.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You’re a proven technical architect with deep expertise in PCIe (Root Complex, Endpoint, and RCiEP) and related IO protocols.
• You’re experienced in SOC integration, including IP sourcing (e.g., Synopsys/Cadence), clock/power domain management, and address translation (MMU, IOMMU, ATS, SR-IOV).
• You understand ordering rules across multiple protocols (PCIe, AXI, CXL) and know how to manage interrupt mechanisms like MSI and MSI-X.
• You’re collaborative, a fast learner, and confident navigating trade-offs even when stakeholders aren’t fully aligned.

What We Need

• Define the IO chiplet architecture, including specifications for self-hosted RISC-V CPUs, AI accelerators, and system-wide connectivity.
• Deliver high-quality architectural definitions across PCIe, AXI/CHI, CXL, and ensure compliance with coherence and ordering models.
• Work on IP integration, ensuring robust interaction across interconnect layers, translation layers (IOMMU, TLB), and virtualization features.
• Help drive execution alignment by influencing teams to adopt architectural strategies and interface standards with minimal friction.

What You Will Learn

• How Tenstorrent is designing next-generation chiplet-based SoCs that unify AI, CPU, and IO elements at scale.
• How advanced interconnects (e.g., UCIe, BoW) and system management interfaces (e.g., BMC) shape the architecture of future platforms.
• How to architect systems that handle heterogeneous processing elements, secure virtualization, and complex software stacks (OS, VMM, Secure Monitor).
• How to lead large architectural decisions and drive alignment across IP, SoC, and system software teams in a high-velocity environment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.