Cadence Design Systems
IC Physical Design Flow, Principal Solutions Engineer - AE
Be an Early Applicant
The role involves providing technical support for Cadence digital design products, guiding customers, conducting presentations, mentoring junior engineers, and continuously improving tools and methodologies.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We offer amazing opportunities to grow, no matter where you are in your career.
The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post–sales activities at advanced nodes for Cadence Digital IC products.
Key Responsibilities
- Provide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff
- Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
- Conduct technical presentations and product demonstrations
- Drive technical evaluations/benchmarks to success
- Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements
- Drive adoption and proliferation of Cadence tools and technologies
- Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
- Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements
- Provide technical support, when developing business case for process improvement projects.
- Provide mentorship to junior engineers
Job Requirements
- Requires a BS or MS in EE with 10-14 years industry related experience in design and EDA (Digital Implementation/Signoff)
- Understands ASIC Design implementation process and steps
- Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler)
- Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler)
- Experience with EDA tools in the IC digital implementation & signoff flows (STA tools)
- Strong STA and SDC debugging abilities are required.
- Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus.
- Automation skills using Perl, Tcl and shell scripting essential
- Strong analytical & analysis skills covering digital implementation is critical.
- Proven track record and experience working in a fast paced environment
- Excellent customer interaction & presentation skills
The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Top Skills
Automation With Tcl
Cadence Technology
Design Closure
Digital Design Implementation
Perl
Place And Route
Shell Scripting
Synthesis
Timing Signoff
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