Lead custom analog and mixed-signal IC layout, including ADCs, DACs, RF components, floorplans, and block-level designs. Minimize parasitic effects through matching, noise isolation, and advanced layout techniques. Ensure compliance with process design rules and foundry specifications, collaborate on manufacturing issue resolution, and develop automation scripts for repetitive layout tasks. The role requires Cadence expertise, post-layout simulation experience, and advanced-node experience below 28nm.
This is a remote position.
ROLE DETAILS :
Industry: manufacturer of Microprocessors with embedded AI
Location : Remote EU or France (Paris) with occasional travel to Head Office
Markets : Worldwide/Internationational
Minimum expérience : 3 years
Environnement :
Cadence tools : Virtuoso and other tools from the Cadence suite
Fine Element analysis tools like Altair SImSolid, Ansys Mechanical, HyperWorks, Femap, ANSYS, Abaqus, Patran, SimScale.
Techniques : Layout automation, Analog layout, analog and mixed-signal circuits, floorplans, block-level layouts, process design rules, ADC Layout, DAC Layout,
Languages : English (mandatory), French is a plus but not mandatory
Your manager : the R&D Director
MISSIONS
As a Layout Engineer within the Analog IC team you will :
Lead the layout of custom ICs and analog components while developing automation tools.
Design and implement custom layouts for analog and mixed-signal circuits, including custom analog and RF components, while minimizing parasitic effects to enhance the DC and AC precision of analog signals.
Create floorplans and block-level layouts for high-performance analog systems.
Ensure alignment with process design rules and foundry specifications.
Collaborate with foundry engineers to resolve layout-related issues during manufacturing.
Develop and utilize custom scripts or tools to efficiently automate repetitive layout tasks.
Profil
Extensive experience with the physical layout of ADCs, DACs, and other mixed-signal components.
Demonstrated success in completing complex layouts across various node sizes.
In-depth expertise in analog layout techniques, including device matching, parasitic minimization, and noise isolation strategies.
Proficiency with Cadence tools.
Experience in post-layout simulation using FEM tools.
Experience with layout automation is a plus.
Experience in Advanced node required (<28nm),
experience in GF 22FDX is highly valued.
Informations contractuelles
Role type : Permanent. EU remote or based in France with occasional travel to the head office in Paris (1 x every 6 or 8 weeks).
Evolution : Lead and management positions as the company grows
Recruitment process :
1st culture fit interview with a team member
2nd technical interview to assess technical knowledge
Written technical test
Invitation to visit the office and discuss an offer
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