Principal Digital Design Engineer

We’re looking for an experienced Principal Engineer/Manager to lead a small, high-impact team building next-generation cellular infrastructure radio Front Haul Gateway (FHGW) solutions in both FPGA and ASIC. You’ll own everything from architecture through production—defining features, authoring device specifications, and driving the design flow for high-performance programmable logic with embedded Linux-based wireless communications software. This is a senior technical leadership and management role with direct influence on our market-leading cellular infrastructure products, working hands-on alongside experts across design, verification, firmware, and system engineering.

• Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight
• Own solution architecture end-to-end—taking marketing requirements and translating to product specifications through production-quality programmable logic design, verification and hardware validation
• Drive architecture / micro-architecture definition, CPU/bus/memory subsystem design, IP integration, and physical implementation for complex SoC designs
• Collaborate with system engineering on Radio product specifications, ensuring alignment across the company
• Partner with IP, design verification, firmware, software, and production teams to close design issues and meet program milestones
• Refine development methodologies and enforce design quality standards across the team, including simulation, linting, clock-domain crossing checks, and formal verification
• Collaborate with embedded Linux-based wireless communications software team that complements the FPGA/ASIC logic layer

• 20+ years of experience in FPGA and SoC development and mass production, including a proven track record in a technical leadership and management role
• MS or PhD in Electrical Engineering or equivalent
• Deep expertise in Verilog and SystemVerilog, and front-end tooling (simulation, linting, CDC, formal verification)
• Hands-on experience with packet processing designs including buffering, routing, transposing, combining, framing/de-framing packet based formats (e.g. Ethernet, O-RAN/eCPRI, etc)
• Hands-on experience with AMBA AXI/AHB/APB bus protocol specification and implementation
• Proven ability to define constraints, run synthesis and static timing analysis, and own a complete front-to-back AMD (Xilinx Vivado) FPGA implementation flow
• Working knowledge of DFT/DFM, SCAN ATPG, BIST, and fault coverage analysis
• Proficiency in SystemVerilog and other advanced design verification methodologies
• Comfort with scripting and programming languages including C/C++, Perl, Tcl, and Python
• Strong communication and presentation skills; ability to drive results under aggressive schedules across cross-functional teams

• Experience developing cellular infrastructure radio products, particularly 10/25Gbps Ethernet eCPRI connectivity to the DU and interface to RF ASICs.
• Familiarity with O-RAN FS7.2x specifications or eCPRI/CPRI front haul protocols
• Understanding of Array based radios including AAU and mMIMO
• Exposure to AI-assisted EDA tools for synthesis, timing analysis, or verification (e.g., AI-driven placement/routing assistants, ML-based timing closure prediction, AI-guided power analysis)
• Experience using Claude Code or similar AI coding assistants to accelerate design scripting, documentation, or code review — familiarity with agentic AI tools for engineering workflows is a genuine differentiator
• Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general-purpose LLMs prompted for Verilog/SystemVerilog generation and review)
• Comfort using AI tools for verification productivity — assertion generation, coverage analysis, or ML-based bug prediction to speed up simulation closure
• Experience applying AI to technical documentation workflows — LLM-assisted datasheet parsing, specification drafting, or design review summarization
• General comfort adopting AI-augmented workflows to boost design productivity

At InnoPhase, dba GreenWave Radios, our total rewards package includes both a competitive base salary and pre-IPO stock options. The anticipated base salary range for this position is $190,000 to $225,000 annually. Actual compensation will be determined based on several factors, including market conditions, interview performance, skills, qualifications, experience, education, and geographic location. In addition to base pay, employees are eligible for a comprehensive benefits package. For detailed information on our benefits programs, please visit our website.