Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
As a CPU Design Verification Engineer at Tenstorrent, you will take significant ownership in verifying high-performance, out-of-order RISC-V CPU designs. This role is well-suited for experienced engineers who enjoy deep technical problem-solving, influencing verification strategy, and collaborating closely with architects and micro-architects to ensure correctness, performance, and scalability of complex CPUs.
This role is remote, based out of North America.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- You are passionate about computer architecture and design verification.
- You have demonstrated experience applying one or more design verification methodologies to CPU or GPU or complex Soc verification.
- Comfortable owning large functional areas and driving verification from concept through closure.
- Detail-driven and persistent when debugging subtle, cross-module architectural issues.
- Collaborative by nature, able to work effectively with architects, designers, and other verification engineers.
What We Need
- 5–15 years of industry experience in design verification of CPUs, GPUs, or complex SoCs.
- Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field.
- Strong understanding of computer architecture and out-of-order CPU microarchitecture.
- Proficiency in creating and executing test plans, from initial feature bring-up to closure, and hands-on experience with portable test-benches, pseudo-random test generators, and emulation.
- Strong programming skills in C++, Python, and System Verilog.
What You Will Learn
- Advanced insights into out-of-order RISC-V CPU microarchitecture and real-world design tradeoffs.
- Scalable verification strategies for high-performance, deeply pipelined CPUs.
- How architecture decisions propagate into verification complexity and coverage requirements.
- Practical experience integrating formal verification, emulation, and simulation at scale.
- Emerging applications of machine learning and AI to improve verification efficiency and debug productivity.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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