Jobs at Broadcom

The ASIC Design Engineer is responsible for leading complex design implementations, ensuring quality through peer reviews, and adapting to technology changes.

The ASIC Design Engineer leads design implementations, ensuring quality in multiple disciplines including synthesis, floorplanning, and timing closure with minimal supervision.

The IC Design Engineer designs and develops integrated circuits, oversees ASIC development, defines architecture, and evaluates processes. Responsibilities include leading product delivery and mentoring junior team members.

Develops and deploys Calibre verification decks for advanced FINFET, GAA, and high-voltage technologies. Defines tool acceptance criteria, creates IP test cases and test structures, automates CAD workflows, supports extraction and simulation tools, resolves EDA and technology-file issues, documents processes, trains design engineers, and evaluates emerging EDA capabilities. The role collaborates with foundries, EDA vendors, and internal engineering teams to support physical verification and post-layout extraction.

Plans, installs, upgrades, maintains, and troubleshoots IBM z/OS, Broadcom, and third-party mainframe software across multiple Sysplexes and LPARs. The role supports government clients, disaster recovery testing, change control, compliance, root-cause analysis, and off-hours maintenance. It also documents implementation plans, coordinates ITSM approvals, resolves vendor issues, and mentors government employees and junior technical staff. An active Secret clearance and recent CompTIA certification are required.

Lead planning, execution, monitoring, control, and closure of technical consulting projects. Serve as primary client contact, apply project governance, manage scope/staffing/invoicing, mitigate risks, and deliver large or complex mainframe/open-systems IT projects on time and on budget.

Owns system-level test program execution for multiple semiconductor customer programs from silicon bring-up through high-volume production. Responsibilities include schedule, cost, quality, yield, capacity, customer commitments, risk management, Asia production-site leadership, equipment planning, test methodology innovation, root-cause analysis, and cross-functional coordination with design, manufacturing, quality, and logistics teams. Requires deep semiconductor test engineering expertise, ATE programming, distributed-team leadership, and periodic international travel.

Provides senior-level technical consulting for mainframe infrastructure environments and Broadcom Software products. Responsibilities include solution architecture, product implementation and upgrades, integrations, demonstrations, proofs of concept, troubleshooting, technical documentation, customer presentations, and post-implementation support. The consultant advises clients and management on infrastructure strategies and works with account teams to design solutions. Requires expertise in z/OS, Broadcom mainframe tools, REXX or HLASM, and major mainframe subsystems and security managers. Client-site travel is required.

Develop and configure UVM testbenches for large SoC designs. Independently manage designs from initial specification through timing closure and physical design handoff, debug verification issues, and collaborate with architecture, verification, and physical design teams to mitigate risks and meet milestones.

Design and architect high-speed 100G+ SerDes signal-processing systems, including equalizers, FEC, filters, modulation, and analog compensation. Develop MATLAB and C/C++ models, simulations, requirements, verification plans, firmware, and lab tests. Collaborate with analog, digital, RTL, firmware, and validation teams to implement and debug ASIC designs. Support communications standards development, customer meetings, technical documentation, and marketing collateral.

Design and develop high-speed analog circuits for electronic systems, conduct tests, analyze data, and select reliable components.

Design, develop, test, debug, and maintain low-level firmware, middleware, applications, diagnostics, and drivers for embedded optical PHY products. Collaborate with system, analog, and digital hardware teams; troubleshoot embedded C code; establish software architecture, coding standards, design patterns, and documentation practices; and help recruit and mentor engineering talent.

Verify high-speed interconnect ASICs throughout the product lifecycle at block and chip levels. Develop and maintain SystemVerilog UVM verification environments, understand IEEE Ethernet standards, collaborate with architecture, design, and firmware teams, and create scripting tools to improve verification efficiency and design quality.

Designs high-speed ASIC blocks for 10Gbps–400Gbps communication systems. Responsibilities include architecture, RTL/HDL coding, timing constraints, verification, synthesis, equivalency checking, CDC and lint reviews, power and design-for-test analysis, scripting, silicon bring-up, lab debugging, and production qualification. Collaborates with distributed engineering teams to define resources, schedules, validation plans, and design tradeoffs.

Designs and validates ASIC blocks for high-speed optical communication physical-layer products. Responsibilities include architecture, RTL coding, lint, CDC, synthesis, equivalence checking, timing analysis, simulation, silicon debug, verification planning, power and area tradeoffs, silicon bring-up, and ATE validation. Requires expertise in ARM subsystems, high-speed digital design, Ethernet and OTN networks, FEC, ASIC development flows, and design-for-power, test, and manufacturing.

Designs and validates high-speed analog and mixed-signal circuitry for data center connectivity applications. Responsibilities include developing novel CMOS circuit techniques, optimizing speed, power, and area, creating circuit models, performing simulation and custom layout, developing test plans, and characterizing and debugging designs for manufacturability. The role also requires analyzing experimental results, selecting reliable components, and understanding broadband communication SoC architectures.

Design and verify analog and mixed-signal IP, including bandgaps, ADCs, DACs, regulators, comparators, and GPIOs. Oversee layout and post-layout SPICE validation, develop Verilog behavioral and gate-level models, deliver EDA views and technical documentation, and guide silicon bring-up and validation. Analyze test data, support laboratory testing, and troubleshoot silicon failures while collaborating across advanced process technologies.

Designs complex front-end RTL IP blocks for leading-edge Ethernet switching silicon used in AI/ML and cloud data centers. Responsibilities include collaborating with global architecture and design teams, developing new device products, and emphasizing design and silicon debug. The role requires strong communication, documentation, self-direction, and teamwork, along with extensive industry experience in RTL design and familiarity with Python or Perl.

Design and execute block- and chip-level verification for high-speed interconnect ASICs. Build SystemVerilog UVM testbenches, validate IEEE Ethernet protocols, understand chip architecture, and create scripts/tools to improve verification efficiency. Collaborate with architecture, firmware, physical and layout teams throughout product development.

Develop and optimize ATE test programs and test hardware for high-speed networking switches. Debug failures, reduce test time, perform volume data analysis, collaborate with design and production teams, and support extreme temperature ASIC testing.