Jobs at Broadcom

Translate schematics into DRC/LVS-clean layouts for critical analog/RF IP blocks, collaborate on floorplanning, power/ground architecture, and device matching, and carry designs from initial floorplan through tape-out using industry EDA tools on advanced FinFET nodes.

The Hardware Engineer will evaluate silicon technology for IP and product designs, focusing on technology assessment, design enablement, and collaboration with foundry and design teams. Responsibilities include test structure layout, simulation, silicon characterization, and ensuring design quality across multiple projects.

Lead import compliance for customs and import operations, ensuring adherence to CBP regulations, HTS classification, valuation, country of origin, duty preference programs, and CTPAT. Manage brokers, documentation, audits, policy development, cross-functional coordination with engineering/logistics/procurement, and training to scale import compliance programs and maintain audit-ready records.

Develop and optimize ATE test programs and test hardware for high-speed networking switches. Debug failures, reduce test time, perform volume data analysis, collaborate with design and production teams, and support extreme temperature ASIC testing.

The Analog Layout Designer will independently execute block and IP level layout designs, coordinate with design teams, and ensure quality through debugging and understanding of analog layout principles.

Design and validate high-speed analog mixed-signal circuitry for data center connectivity, managing complex issues and component selection.

Design and implement low-level firmware for optical PHY chipsets, collaborate with teams, develop firmware applications, and mentor engineering talent.

Contribute to SOC development by architecting verification environments, debugging simulations, writing diagnostics, and utilizing low power silicon verification for mobile applications.

The role involves architecting SOC verification environments, developing test plans, debugging simulations, writing diagnostics for FPGA and ASIC validation, and automating verification flows.

Lead qualification, characterization, and transfer of analog/mixed-signal CMOS ICs from proto to volume production. Perform reliability qualifications (ESD, LU, HTOL, package), PVT product characterization, statistical analysis, and reporting. Drive cross-functional projects for release to production, yield improvement, cost reduction, and customer support. Support package/process qualification, failure analysis, and maintain product quality targets.

Lead digital architecture, design, synthesis and verification of RTL for AMS/IO subsystems. Drive timing closure, lint/CDC debug, formal verification, DFT insertion, and generate timing constraints. Collaborate across analog, verification, and SoC teams, produce specifications and verification plans, and support advanced-node/FinFET designs.

Lead end-to-end silicon diagnostic pipeline using AI/ML to analyze scan failures and process data, build models for failure classification and predictive yield, orchestrate AI-based EDA tools, and drive cross-functional root-cause analysis to improve yield and time-to-market.

The role involves triaging and resolving complex issues with Fibre Channel HBAs, collaborating on product releases, and creating technical documentation to aid customer implementation.

Design mixed-signal and analog integrated circuits focusing on high-speed circuits, clock generation, and data converters. Candidate should hold an MSEE or PhD and have several years of industry experience contributing to IC design projects.

Design and validate high-speed analog mixed-signal integrated circuits for data-center connectivity. Research novel circuit techniques, perform layout and non-ASIC design, characterize and debug for manufacturability, create circuit models and test plans, and work on system-level broadband SoC architectures.

Design and develop memory compilers and circuit blocks, analyze architectures, simulate designs, and debug silicon issues.

The Firmware Engineer will design, develop, debug, and test embedded firmware for networking and storage products, collaborating in a team to support custom firmware features.

Lead and manage customer ASIC programs end-to-end, advise on EDA flows and design best practices, execute physical design checks, assess and mitigate risks, collaborate with cross-functional teams, and support tape-out, bring-up, and production for advanced-node chips.

Lead and manage external customer ASIC programs end-to-end, advise on EDA flows and best practices, perform physical design and STA checks, identify and mitigate design risks, coordinate cross-functional teams (test, packaging, fabrication, bring-up), and communicate technical findings to management and business teams.

Lead customer ASIC programs end-to-end—from RFQ through tape-out and production—guiding physical design, STA, test, packaging and EDA flows. Advise customers, execute physical-design checks, assess and mitigate risks, collaborate cross-functionally, and publish best-practice guidance.