Jobs at Broadcom

Design and optimize analog and mixed-signal IC blocks from behavioral models through transistor-level implementation, layout, verification, characterization, and production test. Lead analog engineering projects, define analog-digital interfaces, review package routing and test boards, analyze noise, distortion, power, and linearity, and debug silicon performance. Collaborate with layout, package, digital, and automatic test engineering teams while documenting circuit operation and performance.

The role involves triaging and resolving complex issues with Fibre Channel HBAs, collaborating on product releases, and creating technical documentation to aid customer implementation.

Perform cyber incident response (detection, containment, remediation), threat hunting, build and tune threat detections, integrate log sources into SIEMs, and develop/manage security automation playbooks using Python and scripting.

Lead planning, execution, monitoring, control, and closure of technical consulting projects. Serve as primary client contact, apply project governance, manage scope/staffing/invoicing, mitigate risks, and deliver large or complex mainframe/open-systems IT projects on time and on budget.

Design and verify high-speed SerDes physical-layer algorithms and architectures (100G+). Develop bit-exact MATLAB and C/C++ system models, run system-level simulations, collaborate with analog/digital teams, perform lab validation and firmware/debug, document requirements and test plans, support standards and customer interactions.

Design and develop memory compilers and circuit blocks, analyze architectures, simulate designs, and debug silicon issues.

The Firmware Engineer will design, develop, debug, and test embedded firmware for networking and storage products, collaborating in a team to support custom firmware features.

Lead IT and operational audit engagements, perform SOX/ITGC testing, assess control deficiencies, support remediation and attestations, coordinate with external auditors, and advise IT/Finance on control improvements and emerging risks such as AI governance.

Provide pre- and post-sales technical support for high-speed interconnect PHY products, debug hardware/firmware/board issues, review schematics/layouts, analyze customer architectures, train customers and FAEs, and support product definition and roadmap to secure customer design wins.

Lead and manage external customer ASIC programs end-to-end, advise on EDA flows and best practices, perform physical design and STA checks, identify and mitigate design risks, coordinate cross-functional teams (test, packaging, fabrication, bring-up), and communicate technical findings to management and business teams.

Lead and manage customer ASIC programs end-to-end, advise on EDA flows and design best practices, execute physical design checks, assess and mitigate risks, collaborate with cross-functional teams, and support tape-out, bring-up, and production for advanced-node chips.

The ASIC Design Engineer is responsible for leading complex design implementations, ensuring quality through peer reviews, and adapting to technology changes.

The ASIC Design Engineer leads design implementations, ensuring quality in multiple disciplines including synthesis, floorplanning, and timing closure with minimal supervision.

Lead constrained-random verification of high-throughput Ethernet ASICs for AI/ML acceleration using SystemVerilog/UVM testbenches, drive coverage closure, run simulations with VCS/Incisive, script automation, collaborate with global design and architecture teams, and provide technical leadership.

The ATE Test Development Engineer will develop ATE test programs for high-speed networking switches, optimize test processes, and debug hardware. Collaborate with cross-functional teams and oversee production release of test programs.

Develop ATE test programs for networking switches, including hardware design, debugging, and optimization. Collaborate with product and design engineers for production release.

Develop and execute verification plans and environments for complex digital and mixed-signal IP. Create UVM testbenches, random and directed tests, assertions, functional models; perform coverage closure, debug RTL and gate-level failures, and collaborate with design teams and EDA vendors. May work with emulation and FPGA prototyping and adopt advanced verification flows.

Design and develop integrated circuits and ASICs: define architecture, logic, and module interfaces; perform system simulation, verification, synthesis, place-and-route, timing and power analysis; contribute to IC layout; evaluate process flow and equipment; run experiments and analyze results; coordinate with vendors and mentor junior staff as needed.

Senior mainframe infrastructure consultant providing architecture, implementation, upgrades, troubleshooting, demos/POCs, and technical leadership for Broadcom mainframe products. Requires coding/scripting (REXX/COBOL/HLASM), deep z/OS expertise, customer engagement, and travel to client sites.

Develop Digital-Mixed Signal models of analog IPs using SystemVerilog, support verification teams, and work with analog circuit design and testbench creation.