Kernel is building world leading, non-invasive brain interface technology.

We are looking for an experienced Design Verification Engineer to join our ASIC development team. Successful applicants will have taped-out/released to market a couple of ASIC/FPGA projects. Experiences with developing/working with modular test benches built for portability and maintainability, as well as test grading is a big plus. 

Neuroscience is the new rocket science.

ESSENTIAL FUNCTIONS:

• Pre-silicon, frontend verification of HDL/RTL modules through simulation
• Documenting verification plans and results
• Development/maintenance of test bench architecture
• Automating simulation-related tasks

BASIC QUALIFICATIONS:

• B.S., Computer Science, Computer Engineering, or Electrical Engineering
• 4+ years of experience in frontend verification of ASIC or FPGA modules
• Proficient in SystemVerilog and UVM libraries
• Proficient in OOP best practices
• Experience in running simulation with multi-module and/or multi-chip test benches
• Experience in developing/enhancing test bench components
• Experience with industry-standard peripheral protocols (e.g. Q/SPI, I2C)
• Proficient in scripting

PREFERRED SKILLS:

• You've participated in an ASIC project from documentation to tape-out
• You like finding and solving problems
• You've worried about simulation performance and maximizing coverage
• You've helped with post-silicon bringup
• You've worked with third-party IPs/VIPs

This position will require access to information protected under U.S. export control laws and regulations, including the International Traffic in Arms Regulations (ITAR) and/or the Export Administration Regulations (EAR). Please note that any offer for employment will be conditioned on authorization to receive software or technology controlled under these U.S. export control laws and regulations without sponsorship for an export license.